From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Andrew Burgess <aburgess@redhat.com>,
Mike Frysinger <vapier@gentoo.org>,
Nick Clifton <nickc@redhat.com>
Cc: binutils@sourceware.org
Subject: [PATCH 14/40] sim/frv: Add explicit casts
Date: Thu, 20 Oct 2022 09:26:00 +0000 [thread overview]
Message-ID: <e1baa1be3601612266dc6ae0bdde8426ff2a42c8.1666257885.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1666257885.git.research_trasio@irq.a4lg.com>
Clang generates a warning if there is an enum value with a mismatching type
without an explicit cast ("-Wenum-conversion").
On the default configuration, it causes a build failure
(unless "--disable-werror" is specified).
This commit adds explicit casts on the FR-V instruction decoder.
Note:
This commit touches CGEN-generated files directly.
Modifying CGEN is the best way to prevent this issue from happening again
but there is another known regression in CGEN to resolve.
---
sim/frv/decode.c | 14 +++++++-------
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/sim/frv/decode.c b/sim/frv/decode.c
index 307b593e148..9c4a97833ad 100644
--- a/sim/frv/decode.c
+++ b/sim/frv/decode.c
@@ -39,12 +39,12 @@ static IDESC frvbf_insn_data[FRVBF_INSN__MAX];
static const struct insn_sem frvbf_insn_sem[] =
{
- { VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY },
- { VIRTUAL_INSN_X_AFTER, FRVBF_INSN_X_AFTER, FRVBF_SFMT_EMPTY },
- { VIRTUAL_INSN_X_BEFORE, FRVBF_INSN_X_BEFORE, FRVBF_SFMT_EMPTY },
- { VIRTUAL_INSN_X_CTI_CHAIN, FRVBF_INSN_X_CTI_CHAIN, FRVBF_SFMT_EMPTY },
- { VIRTUAL_INSN_X_CHAIN, FRVBF_INSN_X_CHAIN, FRVBF_SFMT_EMPTY },
- { VIRTUAL_INSN_X_BEGIN, FRVBF_INSN_X_BEGIN, FRVBF_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_AFTER, FRVBF_INSN_X_AFTER, FRVBF_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEFORE, FRVBF_INSN_X_BEFORE, FRVBF_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CTI_CHAIN, FRVBF_INSN_X_CTI_CHAIN, FRVBF_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_CHAIN, FRVBF_INSN_X_CHAIN, FRVBF_SFMT_EMPTY },
+ { (CGEN_INSN_TYPE) VIRTUAL_INSN_X_BEGIN, FRVBF_INSN_X_BEGIN, FRVBF_SFMT_EMPTY },
{ FRV_INSN_ADD, FRVBF_INSN_ADD, FRVBF_SFMT_ADD },
{ FRV_INSN_SUB, FRVBF_INSN_SUB, FRVBF_SFMT_ADD },
{ FRV_INSN_AND, FRVBF_INSN_AND, FRVBF_SFMT_ADD },
@@ -792,7 +792,7 @@ static const struct insn_sem frvbf_insn_sem[] =
static const struct insn_sem frvbf_insn_sem_invalid =
{
- VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY
+ (CGEN_INSN_TYPE) VIRTUAL_INSN_X_INVALID, FRVBF_INSN_X_INVALID, FRVBF_SFMT_EMPTY
};
/* Initialize an IDESC from the compile-time computable parts. */
--
2.34.1
next prev parent reply other threads:[~2022-10-20 9:29 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 9:25 [PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1) Tsukasa OI
2022-10-20 9:25 ` [PATCH 01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib Tsukasa OI
2022-10-20 9:25 ` [PATCH 02/40] sim: Check known getrusage declaration existence Tsukasa OI
2022-10-20 9:25 ` [PATCH 03/40] sim/aarch64: Remove unused functions Tsukasa OI
2022-10-20 9:25 ` [PATCH 04/40] cpu/cris: Initialize some variables on CRIS CPU Tsukasa OI
2022-10-22 1:59 ` Hans-Peter Nilsson
2022-10-20 9:25 ` [PATCH 05/40] cpu/cris: Add u-stall virtual unit to CRIS v32 Tsukasa OI
2022-10-22 1:44 ` Hans-Peter Nilsson
2022-10-20 9:25 ` [PATCH 06/40] sim/cris: Move declarations of f_specific_init Tsukasa OI
2022-10-22 1:46 ` Hans-Peter Nilsson
2022-10-20 9:25 ` [PATCH 07/40] sim/cris: Regenerate with CGEN Tsukasa OI
2022-10-22 2:02 ` Hans-Peter Nilsson
2022-10-20 9:25 ` [PATCH 08/40] sim/erc32: Insert void parameter Tsukasa OI
2022-10-20 9:25 ` [PATCH 09/40] sim/erc32: Use int32_t as event callback argument Tsukasa OI
2022-10-20 9:25 ` [PATCH 10/40] sim/erc32: Use int32_t as IRQ " Tsukasa OI
2022-10-20 9:25 ` [PATCH 11/40] cpu/frv: Initialize some variables Tsukasa OI
2022-10-20 9:25 ` [PATCH 12/40] sim/frv: Initialize nesr variable Tsukasa OI
2022-10-20 9:25 ` [PATCH 13/40] sim/frv: Initialize some variables Tsukasa OI
2022-10-20 9:26 ` Tsukasa OI [this message]
2022-10-20 9:26 ` [PATCH 15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments Tsukasa OI
2022-10-25 13:54 ` Jeff Law
2022-10-20 9:26 ` [PATCH 16/40] sim/lm32: fix some missing function declaration warnings Tsukasa OI
2022-10-20 9:26 ` [PATCH 17/40] sim/lm32: Add explicit casts Tsukasa OI
2022-10-20 9:32 ` [PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1) Tsukasa OI
2022-10-22 19:01 ` Mike Frysinger
2022-10-24 7:59 ` Tsukasa OI
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