From: Tsukasa OI <research_trasio@irq.a4lg.com>
To: Tsukasa OI <research_trasio@irq.a4lg.com>,
Andrew Burgess <aburgess@redhat.com>,
Mike Frysinger <vapier@gentoo.org>,
Nick Clifton <nickc@redhat.com>
Cc: binutils@sourceware.org
Subject: [PATCH 15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments
Date: Thu, 20 Oct 2022 09:26:01 +0000 [thread overview]
Message-ID: <5ab303a5bdfc1da7832f8fa22f57678c9ef1a5fa.1666257885.git.research_trasio@irq.a4lg.com> (raw)
In-Reply-To: <cover.1666257885.git.research_trasio@irq.a4lg.com>
Clang generates a warning if there is a redundant self-assignment
("-Wself-assign"). On the default configuration, it causes a build failure
(unless "--disable-werror" is specified).
However, removing self-assignments in step_once function makes the code less
readable. Instead, this commit inserts dummy addition to match the comments
"Value added == 0". This is redundant but will suppress warnings and
matches with other branches better. It will be also optimized away so we
can ignore performance impact on this.
---
sim/h8300/compile.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/sim/h8300/compile.c b/sim/h8300/compile.c
index 9be7dd565a9..f7d8d590b69 100644
--- a/sim/h8300/compile.c
+++ b/sim/h8300/compile.c
@@ -4141,7 +4141,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
res = GET_B_REG (code->src.reg); /* FIXME fetch? */
if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
!h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
- res = res; /* Value added == 0. */
+ res = res + 0x0; /* Value added == 0. */
else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
!h && (10 <= (res & 0xf) && (res & 0xf) <= 15))
res = res + 0x6; /* Value added == 6. */
@@ -4174,7 +4174,7 @@ step_once (SIM_DESC sd, SIM_CPU *cpu)
res = GET_B_REG (code->src.reg); /* FIXME fetch, fetch2... */
if (!c && (0 <= (res >> 4) && (res >> 4) <= 9) &&
!h && (0 <= (res & 0xf) && (res & 0xf) <= 9))
- res = res; /* Value added == 0. */
+ res = res + 0x0; /* Value added == 0. */
else if (!c && (0 <= (res >> 4) && (res >> 4) <= 8) &&
h && (6 <= (res & 0xf) && (res & 0xf) <= 15))
res = res + 0xfa; /* Value added == 0xfa. */
--
2.34.1
next prev parent reply other threads:[~2022-10-20 9:29 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-20 9:25 [PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1) Tsukasa OI
2022-10-20 9:25 ` [PATCH 01/40] gdb/unittests: PR28413, suppress warnings generated by Gnulib Tsukasa OI
2022-10-20 9:25 ` [PATCH 02/40] sim: Check known getrusage declaration existence Tsukasa OI
2022-10-20 9:25 ` [PATCH 03/40] sim/aarch64: Remove unused functions Tsukasa OI
2022-10-20 9:25 ` [PATCH 04/40] cpu/cris: Initialize some variables on CRIS CPU Tsukasa OI
2022-10-22 1:59 ` Hans-Peter Nilsson
2022-10-20 9:25 ` [PATCH 05/40] cpu/cris: Add u-stall virtual unit to CRIS v32 Tsukasa OI
2022-10-22 1:44 ` Hans-Peter Nilsson
2022-10-20 9:25 ` [PATCH 06/40] sim/cris: Move declarations of f_specific_init Tsukasa OI
2022-10-22 1:46 ` Hans-Peter Nilsson
2022-10-20 9:25 ` [PATCH 07/40] sim/cris: Regenerate with CGEN Tsukasa OI
2022-10-22 2:02 ` Hans-Peter Nilsson
2022-10-20 9:25 ` [PATCH 08/40] sim/erc32: Insert void parameter Tsukasa OI
2022-10-20 9:25 ` [PATCH 09/40] sim/erc32: Use int32_t as event callback argument Tsukasa OI
2022-10-20 9:25 ` [PATCH 10/40] sim/erc32: Use int32_t as IRQ " Tsukasa OI
2022-10-20 9:25 ` [PATCH 11/40] cpu/frv: Initialize some variables Tsukasa OI
2022-10-20 9:25 ` [PATCH 12/40] sim/frv: Initialize nesr variable Tsukasa OI
2022-10-20 9:25 ` [PATCH 13/40] sim/frv: Initialize some variables Tsukasa OI
2022-10-20 9:26 ` [PATCH 14/40] sim/frv: Add explicit casts Tsukasa OI
2022-10-20 9:26 ` Tsukasa OI [this message]
2022-10-25 13:54 ` [PATCH 15/40] sim/h8300: Add "+ 0x0" to avoid self-assignments Jeff Law
2022-10-20 9:26 ` [PATCH 16/40] sim/lm32: fix some missing function declaration warnings Tsukasa OI
2022-10-20 9:26 ` [PATCH 17/40] sim/lm32: Add explicit casts Tsukasa OI
2022-10-20 9:32 ` [PATCH 00/40] sim+gdb: Suppress warnings if built with Clang (big batch 1) Tsukasa OI
2022-10-22 19:01 ` Mike Frysinger
2022-10-24 7:59 ` Tsukasa OI
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