From: Usha Gupta <usha.nitt@gmail.com>
To: cgen <cgen@sourceware.org>
Subject: Help needed for porting opcodes for CISC architecture
Date: Mon, 03 Feb 2014 17:35:00 -0000 [thread overview]
Message-ID: <CANcummWUhCCPZsVRR9EaeZ7Y4o0kK1E4bv9r48qBvPUych2yjA@mail.gmail.com> (raw)
Hi All ,
I am new to CGEN and want to port binutils for a CISC architecture
wherein the instruction length can vary from 1 byte to a maximum of
5-bytes.
I am having trouble porting opcodes using CGEN.
I have defined various hardware elements and instruction fields.
I am not sure what should be the values of
(default-insn-bitsize 8)
(base-insn-bitsize 16)
(default-insn-word-bitsize 16 )
(word-bitsize 16 )
As mentioned in the CGEN manual, I specified default-insn bitsize as
8 (smallest instruction length) and rest of the values as 16 ( word
length is 2 bytes).
This works for 16-bit instructions where both the operands are
explicit in the instruction encoding.
Another important thing to mention here is that the machine does not
have a fixed length opcode.
Here are some of the instruction formats :
1-byte instruction:
1) IIIIIrrr - 5 bits opcode , 3 bits for register operand (one of
the operand is fixed register, implied from the opcode)
2) IIIddddd - 3 bits opcode, 5 bit displacement
2-byte instruction:
1) IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register operand
(source), 5-bit opcode, 3-bit register operand (destination)
How do I define instructions of varying length?
Any help is appreciated.
Thanks and Regards,
Usha Gupta
next reply other threads:[~2014-02-03 17:35 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-03 17:35 Usha Gupta [this message]
2014-02-10 21:31 ` Frank Ch. Eigler
2014-02-17 9:11 ` Usha Gupta
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