From: fche@redhat.com (Frank Ch. Eigler)
To: Usha Gupta <usha.nitt@gmail.com>
Cc: cgen <cgen@sourceware.org>
Subject: Re: Help needed for porting opcodes for CISC architecture
Date: Mon, 10 Feb 2014 21:31:00 -0000 [thread overview]
Message-ID: <y0mlhxipscw.fsf@fche.csb> (raw)
In-Reply-To: <CANcummWUhCCPZsVRR9EaeZ7Y4o0kK1E4bv9r48qBvPUych2yjA@mail.gmail.com> (Usha Gupta's message of "Mon, 3 Feb 2014 23:04:52 +0530")
Usha Gupta <usha.nitt@gmail.com> writes:
> [...]
> (default-insn-bitsize 8)
> (base-insn-bitsize 16)
> (default-insn-word-bitsize 16 )
> (word-bitsize 16 )
OK (though you might need to raise base-insn-bitsize).
> [...]
> Here are some of the instruction formats :
>
> 1-byte instruction:
> 1) IIIIIrrr - 5 bits opcode , 3 bits for register operand (one of
> the operand is fixed register, implied from the opcode)
> 2) IIIddddd - 3 bits opcode, 5 bit displacement
>
> 2-byte instruction:
> 1) IIIIIsss IIIIIttt - 5-bit opcode, 3-bit register operand
> (source), 5-bit opcode, 3-bit register operand (destination)
>
> How do I define instructions of varying length?
Presumably those IIIII's don't overlap - i.e., the hardware can tell
from the first byte that it's a 2-byte instruction (and more opcode
bits need to be fetched). In cgen, instruction opcodes need not be
single fields nor contiguous; just specify one ifield per unique
opcode piece.
- FChE
next prev parent reply other threads:[~2014-02-10 21:31 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2014-02-03 17:35 Usha Gupta
2014-02-10 21:31 ` Frank Ch. Eigler [this message]
2014-02-17 9:11 ` Usha Gupta
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