Incorrect /proc/cpuinfo for AMD A6-9220

Incorrect /proc/cpuinfo for AMD A6-9220

[Jeffrey Walton]

Hi Everyone,

I'm working on an AMD A6-9220 and seeing unusual results from
/proc/cpuinfo. I think this may be an issue with the latest Cygwin. It
may be present in earlier versions, too.

Russinovich's coreinfo shows
(https://docs.microsoft.com/en-us/sysinternals/downloads/coreinfo)
shows below.

Jeff

***** /proc/cpuinfo *****

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Re: Incorrect /proc/cpuinfo for AMD A6-9220

[Jeffrey Walton]

Please disregard. I fat fingered the mouse pad and sent it too early.

On Thu, Apr 12, 2018 at 10:56 PM, Jeffrey Walton <noloader@gmail.com> wrote:
> Hi Everyone,
>
> I'm working on an AMD A6-9220 and seeing unusual results from
> /proc/cpuinfo. I think this may be an issue with the latest Cygwin. It
> may be present in earlier versions, too.
>
> Russinovich's coreinfo shows
> (https://docs.microsoft.com/en-us/sysinternals/downloads/coreinfo)
> shows below.
>
> Jeff
>
> ***** /proc/cpuinfo *****

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Re: Incorrect /proc/cpuinfo for AMD A6-9220

[Brian Inglis]

On 2018-04-16 01:59, Corinna Vinschen wrote:
> On Apr 13 20:36, Jeffrey Walton wrote:
>> On Fri, Apr 13, 2018 at 7:51 AM, Corinna Vinschen wrote:
>>> On Apr 12 23:01, Jeffrey Walton wrote:
>>>> I'm working on an AMD A6-9220 and seeing unusual results from
>>>> /proc/cpuinfo. I think this may be an issue with the latest Cygwin. It
>>>> may be present in earlier versions, too.
>>>> Russinovich's coreinfo is shown below
>>>> (https://docs.microsoft.com/en-us/sysinternals/downloads/coreinfo).
>>>> Notice /proc/cpuinfo is missing aesni, pclmul, rdrand, SSE4.1, SSE4.2,
>>>> AVX, etc.

also AMD missing flags monitor, popcnt, power management constant|invariant tsc;
AMD cache size shown is 0, instead of the sum of L2+L3; AMD cpuid level shown is
the number of standard functions, instead of the total number of standard and
extended non-zero function results

>>> Note that, in theory, cpuinfo has to be extended for each new CPU
>>> generation.  That's a lot of work for marginal gain (Cygwin's not a real
>>> kernel) so I'm doing this only very seldomly.
>>> Patches welcome, of course!
>> I think I found the file of interest at fhandler_proc.cc.
>> Whitespace is a bit off. It is a mix of tabs and space:
>>       if (features1 & (1 << 0))
>>     print (" fpu");
>>       if (features1 & (1 << 1))
>>     print (" vme");
>> Should I perform a whitespace check-in before things begin? Or can you
>> knock it out?
> Whitespacing looks correct to me.  In vim speak, ts=8, sw=2.

also for vim, soft tab stop "sts=2" adds 2 spaces per tab input, avoids
backspacing if you type tabs

-- 
Take care. Thanks, Brian Inglis, Calgary, Alberta, Canada

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Re: Incorrect /proc/cpuinfo for AMD A6-9220

[Corinna Vinschen]

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On Apr 13 20:36, Jeffrey Walton wrote:
> On Fri, Apr 13, 2018 at 7:51 AM, Corinna Vinschen
> <corinna-cygwin@cygwin.com> wrote:
> > On Apr 12 23:01, Jeffrey Walton wrote:
> >> Hi Everyone,
> >>
> >> I'm working on an AMD A6-9220 and seeing unusual results from
> >> /proc/cpuinfo. I think this may be an issue with the latest Cygwin. It
> >> may be present in earlier versions, too.
> >>
> >> Russinovich's coreinfo is shown below
> >> (https://docs.microsoft.com/en-us/sysinternals/downloads/coreinfo).
> >> Notice /proc/cpuinfo is missing aesni, pclmul, rdrand, SSE4.1, SSE4.2,
> >> AVX, etc.
> >
> > Note that, in theory, cpuinfo has to be extended for each new CPU
> > generation.  That's a lot of work for marginal gain (Cygwin's not a real
> > kernel) so I'm doing this only very seldomly.
> >
> > Patches welcome, of course!
> 
> Thanks Corinna. I think I found the file of interest at fhandler_proc.cc.
> 
> Whitespace is a bit off. It is a mix of tabs and space:
> 
>       if (features1 & (1 << 0))
>     print (" fpu");
>       if (features1 & (1 << 1))
>     print (" vme");
> 
> Should I perform a whitespace check-in before things begin? Or can you
> knock it out?

Whitespacing looks correct to me.  In vim speak, ts=8, sw=2.

Just add what you think is missing (make sure it matches AMD/Intel),
but stick to the whitespacing of the existing code.  Please check
https://cygwin.com/contrib.html.


Thanks,
Corinna

-- 
Corinna Vinschen                  Please, send mails regarding Cygwin to
Cygwin Maintainer                 cygwin AT cygwin DOT com
Red Hat

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Re: Incorrect /proc/cpuinfo for AMD A6-9220

[Jeffrey Walton]

On Fri, Apr 13, 2018 at 7:51 AM, Corinna Vinschen
<corinna-cygwin@cygwin.com> wrote:
> On Apr 12 23:01, Jeffrey Walton wrote:
>> Hi Everyone,
>>
>> I'm working on an AMD A6-9220 and seeing unusual results from
>> /proc/cpuinfo. I think this may be an issue with the latest Cygwin. It
>> may be present in earlier versions, too.
>>
>> Russinovich's coreinfo is shown below
>> (https://docs.microsoft.com/en-us/sysinternals/downloads/coreinfo).
>> Notice /proc/cpuinfo is missing aesni, pclmul, rdrand, SSE4.1, SSE4.2,
>> AVX, etc.
>
> Note that, in theory, cpuinfo has to be extended for each new CPU
> generation.  That's a lot of work for marginal gain (Cygwin's not a real
> kernel) so I'm doing this only very seldomly.
>
> Patches welcome, of course!

Thanks Corinna. I think I found the file of interest at fhandler_proc.cc.

Whitespace is a bit off. It is a mix of tabs and space:

      if (features1 & (1 << 0))
    print (" fpu");
      if (features1 & (1 << 1))
    print (" vme");

Should I perform a whitespace check-in before things begin? Or can you
knock it out?

Jeff

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Re: Incorrect /proc/cpuinfo for AMD A6-9220

[Corinna Vinschen]

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On Apr 12 23:01, Jeffrey Walton wrote:
> Hi Everyone,
> 
> I'm working on an AMD A6-9220 and seeing unusual results from
> /proc/cpuinfo. I think this may be an issue with the latest Cygwin. It
> may be present in earlier versions, too.
> 
> Russinovich's coreinfo is shown below
> (https://docs.microsoft.com/en-us/sysinternals/downloads/coreinfo).
> Notice /proc/cpuinfo is missing aesni, pclmul, rdrand, SSE4.1, SSE4.2,
> AVX, etc.

Note that, in theory, cpuinfo has to be extended for each new CPU
generation.  That's a lot of work for marginal gain (Cygwin's not a real
kernel) so I'm doing this only very seldomly.

Patches welcome, of course!


Corinna

-- 
Corinna Vinschen                  Please, send mails regarding Cygwin to
Cygwin Maintainer                 cygwin AT cygwin DOT com
Red Hat

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Incorrect /proc/cpuinfo for AMD A6-9220

[Jeffrey Walton]

Hi Everyone,

I'm working on an AMD A6-9220 and seeing unusual results from
/proc/cpuinfo. I think this may be an issue with the latest Cygwin. It
may be present in earlier versions, too.

Russinovich's coreinfo is shown below
(https://docs.microsoft.com/en-us/sysinternals/downloads/coreinfo).
Notice /proc/cpuinfo is missing aesni, pclmul, rdrand, SSE4.1, SSE4.2,
AVX, etc.

Jeff

***** Coreinfo *****

C:\Users\Test>coreinfo

Coreinfo v3.31 - Dump information on system CPU and memory topology
Copyright (C) 2008-2014 Mark Russinovich
Sysinternals - www.sysinternals.com

AMD A6-9220e RADEON R4, 5 COMPUTE CORES 2C+3G
AMD64 Family 21 Model 112 Stepping 0, AuthenticAMD
Microcode signature: 06006704
HTT             *       Multicore
HYPERVISOR      -       Hypervisor is present
VMX             -       Supports Intel hardware-assisted virtualization
SVM             *       Supports AMD hardware-assisted virtualization
X64             *       Supports 64-bit mode

SMX             -       Supports Intel trusted execution
SKINIT          *       Supports AMD SKINIT

NX              *       Supports no-execute page protection
SMEP            *       Supports Supervisor Mode Execution Prevention
SMAP            -       Supports Supervisor Mode Access Prevention
PAGE1GB         *       Supports 1 GB large pages
PAE             *       Supports > 32-bit physical addresses
PAT             *       Supports Page Attribute Table
PSE             *       Supports 4 MB pages
PSE36           *       Supports > 32-bit address 4 MB pages
PGE             *       Supports global bit in page tables
SS              -       Supports bus snooping for cache operations
VME             *       Supports Virtual-8086 mode
RDWRFSGSBASE    *       Supports direct GS/FS base access

FPU             *       Implements i387 floating point instructions
MMX             *       Supports MMX instruction set
MMXEXT          *       Implements AMD MMX extensions
3DNOW           -       Supports 3DNow! instructions
3DNOWEXT        -       Supports 3DNow! extension instructions
SSE             *       Supports Streaming SIMD Extensions
SSE2            *       Supports Streaming SIMD Extensions 2
SSE3            *       Supports Streaming SIMD Extensions 3
SSSE3           *       Supports Supplemental SIMD Extensions 3
SSE4a           *       Supports Streaming SIMDR Extensions 4a
SSE4.1          *       Supports Streaming SIMD Extensions 4.1
SSE4.2          *       Supports Streaming SIMD Extensions 4.2

AES             *       Supports AES extensions
AVX             *       Supports AVX intruction extensions
FMA             *       Supports FMA extensions using YMM state
MSR             *       Implements RDMSR/WRMSR instructions
MTRR            *       Supports Memory Type Range Registers
XSAVE           *       Supports XSAVE/XRSTOR instructions
OSXSAVE         *       Supports XSETBV/XGETBV instructions
RDRAND          *       Supports RDRAND instruction
RDSEED          -       Supports RDSEED instruction

CMOV            *       Supports CMOVcc instruction
CLFSH           *       Supports CLFLUSH instruction
CX8             *       Supports compare and exchange 8-byte instructions
CX16            *       Supports CMPXCHG16B instruction
BMI1            *       Supports bit manipulation extensions 1
BMI2            *       Supports bit manipulation extensions 2
ADX             -       Supports ADCX/ADOX instructions
DCA             -       Supports prefetch from memory-mapped device
F16C            *       Supports half-precision instruction
FXSR            *       Supports FXSAVE/FXSTOR instructions
FFXSR           *       Supports optimized FXSAVE/FSRSTOR instruction
MONITOR         *       Supports MONITOR and MWAIT instructions
MOVBE           *       Supports MOVBE instruction
ERMSB           -       Supports Enhanced REP MOVSB/STOSB
PCLMULDQ        *       Supports PCLMULDQ instruction
POPCNT          *       Supports POPCNT instruction
LZCNT           *       Supports LZCNT instruction
SEP             *       Supports fast system call instructions
LAHF-SAHF       *       Supports LAHF/SAHF instructions in 64-bit mode
HLE             -       Supports Hardware Lock Elision instructions
RTM             -       Supports Restricted Transactional Memory instructions

DE              *       Supports I/O breakpoints including CR4.DE
DTES64          -       Can write history of 64-bit branch addresses
DS              -       Implements memory-resident debug buffer
DS-CPL          -       Supports Debug Store feature with CPL
PCID            -       Supports PCIDs and settable CR4.PCIDE
INVPCID         -       Supports INVPCID instruction
PDCM            -       Supports Performance Capabilities MSR
RDTSCP          *       Supports RDTSCP instruction
TSC             *       Supports RDTSC instruction
TSC-DEADLINE    -       Local APIC supports one-shot deadline timer
TSC-INVARIANT   *       TSC runs at constant rate
xTPR            -       Supports disabling task priority messages

EIST            -       Supports Enhanced Intel Speedstep
ACPI            -       Implements MSR for power management
TM              -       Implements thermal monitor circuitry
TM2             -       Implements Thermal Monitor 2 control
APIC            *       Implements software-accessible local APIC
x2APIC          -       Supports x2APIC

CNXT-ID         -       L1 data cache mode adaptive or BIOS

MCE             *       Supports Machine Check, INT18 and CR4.MCE
MCA             *       Implements Machine Check Architecture
PBE             -       Supports use of FERR#/PBE# pin

PSN             -       Implements 96-bit processor serial number

PREFETCHW       *       Supports PREFETCHW instruction

Maximum implemented CPUID leaves: 0000000D (Basic), 8000001E (Extended).

Logical to Physical Processor Map:
*-  Physical Processor 0
-*  Physical Processor 1

***** /proc/cpuinfo *****

$ cat /proc/cpuinfo
processor       : 0
vendor_id       : AuthenticAMD
cpu family      : 21
model           : 112
model name      : AMD A6-9220e RADEON R4, 5 COMPUTE CORES 2C+3G
stepping        : 0
cpu MHz         : 1597.000
cache size      : 0 KB
physical id     : 0
siblings        : 2
core id         : 0
cpu cores       : 1
apicid          : 0
initial apicid  : 0
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext
fxsr_opt pdpe1gb rdtscp lm pni cx16 lahf_lm cmp_legacy svm extapic
cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs sse5 skinit
wdt lwp fma4 tce nodeid_msr tbm perfctr_core perfctr_nb
clflush size    : 64
cache_alignment : 64
address sizes   : 48 bits physical, 48 bits virtual
power management: ts ttp tm 100mhzsteps hwpstate cpb eff_freq_ro

processor       : 1
vendor_id       : AuthenticAMD
cpu family      : 21
model           : 112
model name      : AMD A6-9220e RADEON R4, 5 COMPUTE CORES 2C+3G
stepping        : 0
cpu MHz         : 1597.000
cache size      : 0 KB
physical id     : 0
siblings        : 2
core id         : 0
cpu cores       : 1
apicid          : 1
initial apicid  : 1
fpu             : yes
fpu_exception   : yes
cpuid level     : 13
wp              : yes
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush mmx fxsr sse sse2 ht syscall nx mmxext
fxsr_opt pdpe1gb rdtscp lm pni cx16 lahf_lm cmp_legacy svm extapic
cr8_legacy abm sse4a misalignsse 3dnowprefetch osvw ibs sse5 skinit
wdt lwp fma4 tce nodeid_msr tbm perfctr_core perfctr_nb
clflush size    : 64
cache_alignment : 64
address sizes   : 48 bits physical, 48 bits virtual
power management: ts ttp tm 100mhzsteps hwpstate cpb eff_freq_ro

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