Re: [ECOS] PowerPC FEC problems

Re: [ECOS] PowerPC FEC problems

[ken king]

--- Gary Thomas <gary@mlbassoc.com> wrote:


> What revision of the processor (not just model) do
> you have?
> You can read this off the chip, or by printing the
> value of
> the PVR SPR.
> 
> -- 

 mfspr 3,638
yeilds 0xfa200801
where 0x08 is the part number
and 0x01 is the mask number
>
------------------------------------------------------------
> Gary Thomas                 |  Consulting for the
> MLB Associates              |    Embedded world
>
------------------------------------------------------------
> 
> 
> -- 
> Before posting, please read the FAQ:
> http://ecos.sourceware.org/fom/ecos
> and search the list archive:
> http://ecos.sourceware.org/ml/ecos-discuss
> 
> 

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Re: [ECOS] PowerPC FEC problems

[Gary Thomas]

On Fri, 2005-05-06 at 16:15 -0700, ken king wrote:
> IT WORKED!!!! (once anyway)
> 
> Much thanks to Mr. Andrew Lunn for telling me to
> read the data book. And to Mr.Gary Thomas for
> confidence, you told me the driver worked.
> 
> There are two statements in the FEC description
> that probably should be in bold type:
> 
> 1--The DB and buffers must be in external memory.
> Apparently that means, for this version of this
> part, they can not be in EPPC memory.
> 
> 2--Something like, to save overhead the FEC DMA
> uses burst. Apparently that means the the DB and
> Buffers MUST be in burstable memory.

What revision of the processor (not just model) do you have?
You can read this off the chip, or by printing the value of
the PVR SPR.

-- 
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------


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Re: [ECOS] PowerPC FEC problems

[ken king]

IT WORKED!!!! (once anyway)

Much thanks to Mr. Andrew Lunn for telling me to
read the data book. And to Mr.Gary Thomas for
confidence, you told me the driver worked.

There are two statements in the FEC description
that probably should be in bold type:

1--The DB and buffers must be in external memory.
Apparently that means, for this version of this
part, they can not be in EPPC memory.

2--Something like, to save overhead the FEC DMA
uses burst. Apparently that means the the DB and
Buffers MUST be in burstable memory.

I set breakpoints in fec_eth_send() and manually
pointed the DB and buffers to a burstable
location. Packet sent, No bus error, FEC didn't
turn itself off.

Question: Is there a simple way to force these
buffers and BD into another memory location?

I put a static RAM on this board so I could
hopefully use a BDM to download and debug without
having UPM for DRAM programmed or flash drivers
working (it worked well up to now). Note that just
changing the CS (BRx & ORx) is not a good option
as I currently need this RAM to program the UPMs
(that can change when I make things ROMable).

Thanks for all your help so far,
kk


		
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Re: [ECOS] PowerPC FEC problems

[Gary Thomas]

On Fri, 2005-05-06 at 08:26 -0700, ken king wrote:
> --- Andrew Lunn <andrew@lunn.ch> wrote:
> > > > Check the addresses you are using from receive
> > and
> > > > transmit buffers.
> > > > Do you remember to map the virtual addresses
> > into
> > > > bus addresses before
> > > > programming them into the ethernet device? Does
> > > > memory realy exist at
> > > > the address? 
> > > > 
> > > >         Andrew
> > > > 
> > > > -- 
> > > > Before posting, please read the FAQ:
> > > > http://ecos.sourceware.org/fom/ecos
> > > > and search the list archive:
> > > > http://ecos.sourceware.org/ml/ecos-discuss
> > > > 
> > > Yes, I can dump memory around the BDs (Buffer
> > > descriptors) and they look correct. The memory
> > > pointed to by the BD can also be dumped and it
> > > has the same contents as displayed on the
> > > console if eth debugging is on, i.e looks like the
> > > bootp frames. I can put a scope on the PHYs
> > > tx_clock and tx_en -- the clock is running, but
> > > tx_en is never asserted.
> > 
> > You can look at the memory from the processor, so
> > you know you have
> > the correct virtual address. However, the DMA might
> > not be using the
> > virtual address. It will be using some bus address.
> > Bus addresses can
> > be different from virtual addresses. Read the
> > datasheet and see what
> > it says about the addresses to be used for
> > programming the DMA engine.
> > 
> >         Andrew
> I thought that the MMU was off -- the config tool has
> it grayed out. However the MMU is on. Just for fun, I
> disabled it. It would appear that physical addr =
> virtual addr. I still get the bus error after
> verifying the MMU is disabled before and after. I also
> checked that the BDs are correct before and after.
> 

Correct.  The MMU has to be on for this processor in order to
provide proper cache control.  It should be mapped 1-1, so there
is no difference in addresses that the CPU sees vs what the CPM
(FEC) sees.

> As for the data book, it doesnt say much about the
> FEC DMA  it seems to imply that it is different from
> the SDMA which got its own section.

The FEC is its own beast - it does not use any other DMA engine.

Make sure that your Tx buffer descriptor ring is correct and has
been fully initialized.  When you execute the fec->TxUpdate=1
instruction, that tells the FEC to scan for work.

Have you done anything special to your port or the driver?  This
code is known to work on a number of CPUs, including the 852T.


-- 
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------


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Re: [ECOS] PowerPC FEC problems

[ken king]

[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #1: Type: text/plain; charset=us-ascii, Size: 2225 bytes --]


--- Andrew Lunn <andrew@lunn.ch> wrote:
> > > Check the addresses you are using from receive
> and
> > > transmit buffers.
> > > Do you remember to map the virtual addresses
> into
> > > bus addresses before
> > > programming them into the ethernet device? Does
> > > memory realy exist at
> > > the address? 
> > > 
> > >         Andrew
> > > 
> > > -- 
> > > Before posting, please read the FAQ:
> > > http://ecos.sourceware.org/fom/ecos
> > > and search the list archive:
> > > http://ecos.sourceware.org/ml/ecos-discuss
> > > 
> > Yes, I can dump memory around the BDs (Buffer
> > descriptors) and they look correct. The memory
> > pointed to by the BD can also be dumped and it
> > has the same contents as displayed on the
> > console if eth debugging is on, i.e looks like the
> > bootp frames. I can put a scope on the PHYs
> > tx_clock and tx_en -- the clock is running, but
> > tx_en is never asserted.
> 
> You can look at the memory from the processor, so
> you know you have
> the correct virtual address. However, the DMA might
> not be using the
> virtual address. It will be using some bus address.
> Bus addresses can
> be different from virtual addresses. Read the
> datasheet and see what
> it says about the addresses to be used for
> programming the DMA engine.
> 
>         Andrew
> 
> -- 
> Before posting, please read the FAQ:
> http://ecos.sourceware.org/fom/ecos
> and search the list archive:
> http://ecos.sourceware.org/ml/ecos-discuss
> 
> 
I thought that the MMU was off -- the config tool has
it grayed out. However the MMU is on. Just for fun, I
disabled it. It would appear that physical addr =
virtual addr. I still get the bus error after
verifying the MMU is disabled before and after. I also
checked that the BDs are correct before and after.

As for the data book, it doesn’t say much about the
FEC DMA – it seems to imply that it is different from
the SDMA which got it’s own section.

Thanks,
kk



		
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Re: [ECOS] PowerPC FEC problems

[Andrew Lunn]

> > Check the addresses you are using from receive and
> > transmit buffers.
> > Do you remember to map the virtual addresses into
> > bus addresses before
> > programming them into the ethernet device? Does
> > memory realy exist at
> > the address? 
> > 
> >         Andrew
> > 
> > -- 
> > Before posting, please read the FAQ:
> > http://ecos.sourceware.org/fom/ecos
> > and search the list archive:
> > http://ecos.sourceware.org/ml/ecos-discuss
> > 
> Yes, I can dump memory around the BDs (Buffer
> descriptors) and they look correct. The memory
> pointed to by the BD can also be dumped and it
> has the same contents as displayed on the
> console if eth debugging is on, i.e looks like the
> bootp frames. I can put a scope on the PHYs
> tx_clock and tx_en -- the clock is running, but
> tx_en is never asserted.

You can look at the memory from the processor, so you know you have
the correct virtual address. However, the DMA might not be using the
virtual address. It will be using some bus address. Bus addresses can
be different from virtual addresses. Read the datasheet and see what
it says about the addresses to be used for programming the DMA engine.

        Andrew

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Re: [ECOS] PowerPC FEC problems

[ken king]

--- Andrew Lunn <andrew@lunn.ch> wrote:
> On Thu, May 05, 2005 at 07:02:33PM -0700, ken king
> wrote:
> > I have a custom MPC852T board. (note:
> > Custom means porting RedBoot/eCOS and checking
> board
> > out at same time!) I've gotten RedBoot up and
> > almost everything works except ethernet. I
> > started with if_fec.c. The MII interface seems to
> > be working correctly, MDC clock is correct
> > frequency, reasionable data back and forth, etc.
> > 
> > When running gdb and a BDM I get a
> > "Trace/breakpoint" when there is no break point
> > set -- generally a bad thing! I tracked it down
> > to:
> > 
> > fec_eth_send()
> > {
> > ...........
> > 	/* comment out next line --
> > 	** no bad trace/breakpoint*/
> > 	qi->fec->TxUpdate=0x10000;
> > ......
> > 	}
> > 
> > I've written some code to look at the FEC regs
> > before and after the offending line of code.
> > Before, everything looks good. After;
> > 
> > 1-- I_EVENT reg has EB_ERR set -- FEC encountered
> > a bus error.
> > 
> > 2-- Eth Control Reg has eth disabled.
> > 
> > If I #define for buffer descriptors to be in
> > external memory, then the Transfure Error Status
> > Reg (TESR) has IEXT set indicating a /TEA signal
> > was present during a external instruction fetch.
> > /TEA is just connected to a pull-up resistor, I've
> > looked at it with a scope - doesn't look shorted
> > to anything.
> > 
> > So, Long-story-short I think I getting a bus error
> > when the FEC DMA kicks off. Anybody seen this
> > before? Any ideas? What else to look for?
> 
> Check the addresses you are using from receive and
> transmit buffers.
> Do you remember to map the virtual addresses into
> bus addresses before
> programming them into the ethernet device? Does
> memory realy exist at
> the address? 
> 
>         Andrew
> 
> -- 
> Before posting, please read the FAQ:
> http://ecos.sourceware.org/fom/ecos
> and search the list archive:
> http://ecos.sourceware.org/ml/ecos-discuss
> 
Yes, I can dump memory around the BDs (Buffer
descriptors) and they look correct. The memory
pointed to by the BD can also be dumped and it
has the same contents as displayed on the
console if eth debugging is on, i.e looks like the
bootp frames. I can put a scope on the PHYs
tx_clock and tx_en -- the clock is running, but
tx_en is never asserted.

thanks,
kk


		
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Re: [ECOS] PowerPC FEC problems

[Andrew Lunn]

On Thu, May 05, 2005 at 07:02:33PM -0700, ken king wrote:
> I have a custom MPC852T board. (note:
> Custom means porting RedBoot/eCOS and checking board
> out at same time!) I've gotten RedBoot up and
> almost everything works except ethernet. I
> started with if_fec.c. The MII interface seems to
> be working correctly, MDC clock is correct
> frequency, reasionable data back and forth, etc.
> 
> When running gdb and a BDM I get a
> "Trace/breakpoint" when there is no break point
> set -- generally a bad thing! I tracked it down
> to:
> 
> fec_eth_send()
> {
> ...........
> 	/* comment out next line --
> 	** no bad trace/breakpoint*/
> 	qi->fec->TxUpdate=0x10000;
> ......
> 	}
> 
> I've written some code to look at the FEC regs
> before and after the offending line of code.
> Before, everything looks good. After;
> 
> 1-- I_EVENT reg has EB_ERR set -- FEC encountered
> a bus error.
> 
> 2-- Eth Control Reg has eth disabled.
> 
> If I #define for buffer descriptors to be in
> external memory, then the Transfure Error Status
> Reg (TESR) has IEXT set indicating a /TEA signal
> was present during a external instruction fetch.
> /TEA is just connected to a pull-up resistor, I've
> looked at it with a scope - doesn't look shorted
> to anything.
> 
> So, Long-story-short I think I getting a bus error
> when the FEC DMA kicks off. Anybody seen this
> before? Any ideas? What else to look for?

Check the addresses you are using from receive and transmit buffers.
Do you remember to map the virtual addresses into bus addresses before
programming them into the ethernet device? Does memory realy exist at
the address? 

        Andrew

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[ECOS] PowerPC FEC problems

[ken king]

I have a custom MPC852T board. (note:
Custom means porting RedBoot/eCOS and checking board
out at same time!) I've gotten RedBoot up and
almost everything works except ethernet. I
started with if_fec.c. The MII interface seems to
be working correctly, MDC clock is correct
frequency, reasionable data back and forth, etc.

When running gdb and a BDM I get a
"Trace/breakpoint" when there is no break point
set -- generally a bad thing! I tracked it down
to:

fec_eth_send()
{
...........
	/* comment out next line --
	** no bad trace/breakpoint*/
	qi->fec->TxUpdate=0x10000;
......
	}

I've written some code to look at the FEC regs
before and after the offending line of code.
Before, everything looks good. After;

1-- I_EVENT reg has EB_ERR set -- FEC encountered
a bus error.

2-- Eth Control Reg has eth disabled.

If I #define for buffer descriptors to be in
external memory, then the Transfure Error Status
Reg (TESR) has IEXT set indicating a /TEA signal
was present during a external instruction fetch.
/TEA is just connected to a pull-up resistor, I've
looked at it with a scope - doesn't look shorted
to anything.

So, Long-story-short I think I getting a bus error
when the FEC DMA kicks off. Anybody seen this
before? Any ideas? What else to look for?

TIA,
KK

PS Im think of giving up on this FEC thing for a
while. I have one more PHY connected to a SCC,
would you recomend I start with the Adder or QUICC
eth driver?



		
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