[Bug target/100028] New: arm64 failure to generate bfxil

[Bug target/100028] New: arm64 failure to generate bfxil

[luc.vanoostenryck at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

            Bug ID: 100028
           Summary: arm64 failure to generate bfxil
           Product: gcc
           Version: 10.2.0
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: luc.vanoostenryck at gmail dot com
  Target Milestone: ---
            Target: aarch64

Created attachment 50555
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50555&action=edit
should generate bfxil but doesn't

The attached code reproduced here:

#define W       3
#define L       11

int bfxil(int d, int s)
{
        int wmask = (1 << W) - 1;
        return (d & ~wmask) | ((s >> L) & wmask);
}

Should return:
        bfxil:
                bfxil   w0, w1, 11, 3
                ret

but instead returns:
        bfxil:
                ubfx    x1, x1, 11, 3
                and     w0, w0, -8
                orr     w0, w1, w0
                ret

The problem is still present in trunk, was also present in 9.3 but wasn't in
GCC 8.2 (see https://gcc.godbolt.org/z/E6z31hr9r ).

[Bug target/100028] [9/10/11 Regression] arm64 failure to generate bfxil

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
   Target Milestone|---                         |9.4
   Last reconfirmed|                            |2021-04-11
            Summary|arm64 failure to generate   |[9/10/11 Regression] arm64
                   |bfxil                       |failure to generate bfxil

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

[Bug target/100028] [9/10/11 Regression] arm64 failure to generate bfxil

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P2

[Bug target/100028] [9/10/11 Regression] arm64 failure to generate bfxil

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org

--- Comment #2 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Started with r9-3594-g8d2d39587d941a40f25ea0144cceb677df115040

[Bug target/100028] [9/10/11 Regression] arm64 failure to generate bfxil

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |jakub at gcc dot gnu.org
             Status|NEW                         |ASSIGNED

--- Comment #3 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I guess it is basically a dup of PR87763, except that it needs yet another
pattern.
Combiner tries to match here:
    (ior:SI (and:SI (reg:SI 102)
            (const_int -8 [0xfffffffffffffff8]))
        (subreg:SI (zero_extract:DI (subreg:DI (reg:SI 103) 0)
                (const_int 3 [0x3])
                (const_int 11 [0xb])) 0)))
which is similar to:
(define_insn "*aarch64_bfi<GPI:mode>4_noand"
  [(set (match_operand:GPI 0 "register_operand" "=r")
        (ior:GPI (and:GPI (match_operand:GPI 1 "register_operand" "0")
                          (match_operand:GPI 2 "const_int_operand" "n"))
                 (ashift:GPI
                          (match_operand:GPI 3 "register_operand" "r")
                          (match_operand:GPI 4 "aarch64_simd_shift_imm_<mode>"
n"))))]
  "aarch64_masks_and_shift_for_bfi_p (<MODE>mode, UINTVAL (operands[2]),
                                     UINTVAL (operands[4]),
                                     HOST_WIDE_INT_M1U << UINTVAL (operands[4])
)"

[Bug target/100028] [9/10/11 Regression] arm64 failure to generate bfxil

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 50571
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50571&action=edit
gcc11-pr100028.patch

Untested fix.

[Bug target/100028] [9/10/11 Regression] arm64 failure to generate bfxil

[luc.vanoostenryck at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

--- Comment #5 from Luc Van Oostenryck <luc.vanoostenryck at gmail dot com> ---
(In reply to Jakub Jelinek from comment #4)
> Created attachment 50571 [details]
> gcc11-pr100028.patch
> 
> Untested fix.

This solve the few cases I had.
Thanks.

[Bug target/100028] [9/10/11 Regression] arm64 failure to generate bfxil

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:f6ba5d039f988babdd99b5cdfb4557c380e57d69

commit r11-8149-gf6ba5d039f988babdd99b5cdfb4557c380e57d69
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Tue Apr 13 12:43:39 2021 +0200

    aarch64: Restore bfxil optimization [PR100028]

    Similarly to PR87763 for bfi, the GCC 9 combiner changes to not combine
    moves from hard registers regressed the following testcase where we no
    longer recognize bfxil and emit 3 instructions instead.

    The following patch adds define_insn patterns that match what the combiner
    is trying to match in these cases.  I haven't been able to see patterns
    with the other order of the IOR operands, seems the IL is canonicalized
this
    way no matter what is written in the source.

    2021-04-13  Jakub Jelinek  <jakub@redhat.com>

            PR target/100028
            * config/aarch64/aarch64.md (*aarch64_bfxil<mode>_extr,
            *aarch64_bfxilsi_extrdi): New define_insn patterns.

            * gcc.target/aarch64/pr100028.c: New test.

[Bug target/100028] [9/10 Regression] arm64 failure to generate bfxil

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[9/10/11 Regression] arm64  |[9/10 Regression] arm64
                   |failure to generate bfxil   |failure to generate bfxil

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed on the trunk.

[Bug target/100028] [9/10 Regression] arm64 failure to generate bfxil

[luc.vanoostenryck at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

--- Comment #8 from Luc Van Oostenryck <luc.vanoostenryck at gmail dot com> ---
Woks nicely now.
Thanks

[Bug target/100028] [9/10 Regression] arm64 failure to generate bfxil

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|9.4                         |9.5

--- Comment #9 from Richard Biener <rguenth at gcc dot gnu.org> ---
GCC 9.4 is being released, retargeting bugs to GCC 9.5.

[Bug target/100028] [10 Regression] arm64 failure to generate bfxil

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|9.5                         |10.4

--- Comment #10 from Richard Biener <rguenth at gcc dot gnu.org> ---
GCC 9 branch is being closed

[Bug target/100028] [10 Regression] arm64 failure to generate bfxil

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|10.4                        |10.5

--- Comment #11 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
GCC 10.4 is being released, retargeting bugs to GCC 10.5.

[Bug target/100028] [10 Regression] arm64 failure to generate bfxil

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100028

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
      Known to work|                            |11.1.0
   Target Milestone|10.5                        |11.0
             Status|ASSIGNED                    |RESOLVED
      Known to fail|                            |10.5.0

--- Comment #12 from Richard Biener <rguenth at gcc dot gnu.org> ---
Fixed in GCC 11.