[Bug target/100106] New: [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[Bug target/100106] New: [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

            Bug ID: 100106
           Summary: [10/11 Regression] ICE in gen_movdi, at
                    config/arm/arm.md:6187 since r10-2840-g70cdb21e
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

The following fails:

$ cat test.c
union a {
  float _Complex b;
  long long c;
};

void g(union a);

void e() {
  union a f = {1.0f};
  g(f);
}
$ gcc/xgcc -B gcc test.c -c -O
during RTL pass: expand
test.c: In function ‘e’:
test.c:9:11: internal compiler error: in gen_movdi, at config/arm/arm.md:6187
    9 |   union a f = {1.0f};
      |           ^
0x1de9e64 gen_movdi(rtx_def*, rtx_def*)
        /home/alecop01/toolchain/src/gcc/gcc/config/arm/arm.md:6187
0xdb9086 rtx_insn* insn_gen_fn::operator()<rtx_def*, rtx_def*>(rtx_def*,
rtx_def*) const
        /home/alecop01/toolchain/src/gcc/gcc/recog.h:407
0xd8ff58 emit_move_insn_1(rtx_def*, rtx_def*)
        /home/alecop01/toolchain/src/gcc/gcc/expr.c:3766
0xd909ca emit_move_insn(rtx_def*, rtx_def*)
        /home/alecop01/toolchain/src/gcc/gcc/expr.c:3936
0xd69cbb store_bit_field_1
        /home/alecop01/toolchain/src/gcc/gcc/expmed.c:804
0xd6b8bb store_bit_field(rtx_def*, poly_int<1u, unsigned long>, poly_int<1u,
unsigned long>, poly_int<1u, unsigned long>, poly_int<1u, unsigned long>,
machine_mode, rtx_def*, bool)
        /home/alecop01/toolchain/src/gcc/gcc/expmed.c:1183
0xd9eaef store_field
        /home/alecop01/toolchain/src/gcc/gcc/expr.c:7353
0xd95ddf expand_assignment(tree_node*, tree_node*, bool)
        /home/alecop01/toolchain/src/gcc/gcc/expr.c:5482
0xbf2c4e expand_gimple_stmt_1
        /home/alecop01/toolchain/src/gcc/gcc/cfgexpand.c:3910
0xbf303d expand_gimple_stmt
        /home/alecop01/toolchain/src/gcc/gcc/cfgexpand.c:4008
0xbfbaa3 expand_gimple_basic_block
        /home/alecop01/toolchain/src/gcc/gcc/cfgexpand.c:6045
0xbfd954 execute
        /home/alecop01/toolchain/src/gcc/gcc/cfgexpand.c:6729
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

Started with r10-2840-g70cdb21e579191fe9f0f1d45e328908e59c0179e.

[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |arm
           Keywords|                            |ice-on-valid-code
      Known to fail|                            |10.2.1, 11.0
   Target Milestone|---                         |10.4
      Known to work|                            |9.2.1

[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
           Priority|P3                          |P2
   Last reconfirmed|                            |2021-04-16

--- Comment #1 from Richard Biener <rguenth at gcc dot gnu.org> ---
Confirmed.

#1  0x0000000001d9f1c5 in gen_movdi (operand0=0x7ffff63ae390, 
    operand1=0x7ffff63ae480)
    at /home/rguenther/src/trunk/gcc/config/arm/arm.md:6187
6187      gcc_checking_assert (aligned_operand (operands[1], DImode));
(gdb) p debug_rtx (operands[1])
(mem/u/c:DI (reg/f:SI 114) [0  S8 A32])

I think the bug is that

      /* Use the subreg machinery either to narrow OP0 to the required
         words or to cope with mode punning between equal-sized modes.
         In the latter case, use subreg on the rhs side, not lhs.  */
      rtx sub;
      HOST_WIDE_INT regnum;
      poly_uint64 regsize = REGMODE_NATURAL_SIZE (GET_MODE (op0));
      if (known_eq (bitnum, 0U)
          && known_eq (bitsize, GET_MODE_BITSIZE (GET_MODE (op0))))
        {
          sub = simplify_gen_subreg (GET_MODE (op0), value, fieldmode, 0);
          if (sub)
            {
              if (reverse)
                sub = flip_storage_order (GET_MODE (op0), sub);

here simplify_gen_subreg simplifies (subreg:DI ((mem/u/c:SC (reg/f:SI 114) [0 
S8 A32])) to (mem/u/c:DI (reg/f:SI 114) [0  S8 A32]) but SCmode has
different alignment requirement than DImode.

[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |rsandifo at gcc dot gnu.org

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
simplify_subreg has

  /* If we have a SUBREG of a register that we are replacing and we are
     replacing it with a MEM, make a new MEM and try replacing the
     SUBREG with it.  Don't do this if the MEM has a mode-dependent address
     or if we would be widening it.  */

  if (MEM_P (op)
      && ! mode_dependent_address_p (XEXP (op, 0), MEM_ADDR_SPACE (op))
      /* Allow splitting of volatile memory references in case we don't
         have instruction to move the whole thing.  */
      && (! MEM_VOLATILE_P (op)
          || ! have_insn_for (SET, innermode))
      && known_le (outersize, innersize))
    return adjust_address_nv (op, outermode, byte);

at least on STRICT_ALIGN targets I miss an alignment check?  The code is
quite old, of course.

[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[bernd.edlinger at hotmail dot de]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

--- Comment #3 from Bernd Edlinger <bernd.edlinger at hotmail dot de> ---
Yes, indeed something like the following seems to fix the issue:

diff --git a/gcc/simplify-rtx.c b/gcc/simplify-rtx.c
index d13c390..56271e9 100644
--- a/gcc/simplify-rtx.c
+++ b/gcc/simplify-rtx.c
@@ -7217,6 +7217,7 @@ simplify_context::simplify_subreg (machine_mode outermode
          have instruction to move the whole thing.  */
       && (! MEM_VOLATILE_P (op)
          || ! have_insn_for (SET, innermode))
+      && (STRICT_ALIGNMENT && GET_MODE_ALIGNMENT (outermode) < MEM_ALIGN (op))
       && known_le (outersize, innersize))
     return adjust_address_nv (op, outermode, byte);

[Bug target/100106] [10/11/12 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Bernd Edlinger <edlinger@gcc.gnu.org>:

https://gcc.gnu.org/g:c33db31d9ad96f6414460315c12b4b505fad5dd7

commit r12-163-gc33db31d9ad96f6414460315c12b4b505fad5dd7
Author: Bernd Edlinger <bernd.edlinger@hotmail.de>
Date:   Wed Apr 21 14:13:04 2021 +0200

    Fix target/100106 ICE in gen_movdi

    As the test case shows, the outer mode may have a higher alignment
    requirement than the inner mode here.

    2021-04-27  Bernd Edlinger  <bernd.edlinger@hotmail.de>

            PR target/100106
            * simplify-rtx.c (simplify_context::simplify_subreg): Check the
            memory alignment for the outer mode.

            * gcc.c-torture/compile/pr100106.c: New testcase.

[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[edlinger at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

Bernd Edlinger <edlinger at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[10/11/12 Regression] ICE   |[10/11 Regression] ICE in
                   |in gen_movdi, at            |gen_movdi, at
                   |config/arm/arm.md:6187      |config/arm/arm.md:6187
                   |since r10-2840-g70cdb21e    |since r10-2840-g70cdb21e
             Status|NEW                         |ASSIGNED

--- Comment #5 from Bernd Edlinger <edlinger at gcc dot gnu.org> ---
fixed on trunk

[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

--- Comment #6 from Richard Biener <rguenth at gcc dot gnu.org> ---
What about backporting this fix?

[Bug target/100106] [10/11 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by Richard Biener
<rguenth@gcc.gnu.org>:

https://gcc.gnu.org/g:5155015ce57dc133e006f87fdf0237a5f259bebd

commit r11-9786-g5155015ce57dc133e006f87fdf0237a5f259bebd
Author: Bernd Edlinger <bernd.edlinger@hotmail.de>
Date:   Wed Apr 21 14:13:04 2021 +0200

    Fix target/100106 ICE in gen_movdi

    As the test case shows, the outer mode may have a higher alignment
    requirement than the inner mode here.

    2021-04-27  Bernd Edlinger  <bernd.edlinger@hotmail.de>

            PR target/100106
            * simplify-rtx.c (simplify_context::simplify_subreg): Check the
            memory alignment for the outer mode.

            * gcc.c-torture/compile/pr100106.c: New testcase.

    (cherry picked from commit c33db31d9ad96f6414460315c12b4b505fad5dd7)

[Bug target/100106] [10 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

--- Comment #8 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
(In reply to CVS Commits from comment #7)
> The releases/gcc-11 branch has been updated by Richard Biener
> <rguenth@gcc.gnu.org>:
> 
> https://gcc.gnu.org/g:5155015ce57dc133e006f87fdf0237a5f259bebd
> 

Just to note that on master it was necessary to apply r12-3480 as part of a
subsequent patch set.  The problem case was calling gen_highpart() on an
unaligned MEM.  Prior to this patch gen_highpart() would generate the expected
unaligned MEM for the narrower access, but after r12-163 we'd get (subreg(MEM))
being returned, which was unexpected.  I'm not going to backport that now as
it's not clear if this is needed for GCC-11.

[Bug target/100106] [10 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|10.4                        |10.5

--- Comment #9 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
GCC 10.4 is being released, retargeting bugs to GCC 10.5.

[Bug target/100106] [10 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

--- Comment #10 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Alexandre Oliva <aoliva@gcc.gnu.org>:

https://gcc.gnu.org/g:d6b756447cd58bcca20e6892790582308b869817

commit r14-1187-gd6b756447cd58bcca20e6892790582308b869817
Author: Alexandre Oliva <oliva@adacore.com>
Date:   Wed May 24 03:07:56 2023 -0300

    [PR100106] Reject unaligned subregs when strict alignment is required

    The testcase for pr100106, compiled with optimization for 32-bit
    powerpc -mcpu=604 with -mstrict-align expands the initialization of a
    union from a float _Complex value into a load from an SCmode
    constant pool entry, aligned to 4 bytes, into a DImode pseudo,
    requiring 8-byte alignment.

    The patch that introduced the testcase modified simplify_subreg to
    avoid changing the MEM to outermode, but simplify_gen_subreg still
    creates a SUBREG or a MEM that would require stricter alignment than
    MEM's, and lra_constraints appears to get confused by that, repeatedly
    creating unsatisfiable reloads for the SUBREG until it exceeds the
    insn count.

    Avoiding the unaligned SUBREG, expand splits the DImode dest into
    SUBREGs and loads each SImode word of the constant pool with the
    proper alignment.


    for  gcc/ChangeLog

            PR target/100106
            * emit-rtl.cc (validate_subreg): Reject a SUBREG of a MEM that
            requires stricter alignment than MEM's.

    for  gcc/testsuite/ChangeLog

            PR target/100106
            * gcc.target/powerpc/pr100106-sa.c: New.

[Bug target/100106] [10 Regression] ICE in gen_movdi, at config/arm/arm.md:6187 since r10-2840-g70cdb21e

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100106

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|10.5                        |11.3
         Resolution|---                         |FIXED
      Known to fail|                            |10.5.0
             Status|ASSIGNED                    |RESOLVED

--- Comment #11 from Richard Biener <rguenth at gcc dot gnu.org> ---
Fixed in GCC 11.3.