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* [Bug target/101248] New: [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest.
@ 2021-06-29 2:09 crazylht at gmail dot com
2021-06-29 2:12 ` [Bug target/101248] " crazylht at gmail dot com
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: crazylht at gmail dot com @ 2021-06-29 2:09 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101248
Bug ID: 101248
Summary: [AVX512] The upper bits of FIXUPIMMS{S,D} should come
from src1 not dest.
Product: gcc
Version: 12.0
Status: UNCONFIRMED
Keywords: wrong-code
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: crazylht at gmail dot com
Target Milestone: ---
Target: x86_64-*-* i?86-*-*
currently the pattern is defined as
(define_insn "avx512f_sfixupimm<mode>_mask<round_saeonly_name>"
[(set (match_operand:VF_128 0 "register_operand" "=v")
(vec_merge:VF_128
(vec_merge:VF_128
(unspec:VF_128
[(match_operand:VF_128 1 "register_operand" "0")
(match_operand:VF_128 2 "register_operand" "v")
(match_operand:<sseintvecmode> 3
"<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
(match_operand:SI 4 "const_0_to_255_operand")]
UNSPEC_FIXUPIMM)
(match_dup 2)
(const_int 1))
(match_dup 1)
(match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
"TARGET_AVX512F"
"vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_op6>%3, %2,
%0%{%5%}|%0%{%5%}, %2, %<iptr>3<round_saeonly_op6>, %4}";
[(set_attr "prefix" "evex")
(set_attr "mode" "<ssescalarmode>")])
when mask is 1, current GCC will optimize
movl $-1, %eax
kmovw %eax, %k2
vfixupimmpd $0, %xmm2, %xmm1, %xmm0{%k2}
to
vfixupimmsd $0, %xmm3, %xmm1, %xmm0
But the upper 32 bits of vfixupimmsd should come from src1 not dest which means
the upper optimization is wrong.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/101248] [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest.
2021-06-29 2:09 [Bug target/101248] New: [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest crazylht at gmail dot com
@ 2021-06-29 2:12 ` crazylht at gmail dot com
2021-06-29 2:14 ` crazylht at gmail dot com
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: crazylht at gmail dot com @ 2021-06-29 2:12 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101248
--- Comment #1 from Hongtao.liu <crazylht at gmail dot com> ---
src1 here means operands[2], dest here means operand[0] or operands[1].
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/101248] [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest.
2021-06-29 2:09 [Bug target/101248] New: [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest crazylht at gmail dot com
2021-06-29 2:12 ` [Bug target/101248] " crazylht at gmail dot com
@ 2021-06-29 2:14 ` crazylht at gmail dot com
2021-06-30 1:08 ` cvs-commit at gcc dot gnu.org
2021-06-30 1:14 ` crazylht at gmail dot com
3 siblings, 0 replies; 5+ messages in thread
From: crazylht at gmail dot com @ 2021-06-29 2:14 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101248
--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
(In reply to Hongtao.liu from comment #0)
> currently the pattern is defined as
>
> (define_insn "avx512f_sfixupimm<mode>_mask<round_saeonly_name>"
> [(set (match_operand:VF_128 0 "register_operand" "=v")
> (vec_merge:VF_128
> (vec_merge:VF_128
> (unspec:VF_128
> [(match_operand:VF_128 1 "register_operand" "0")
> (match_operand:VF_128 2 "register_operand" "v")
> (match_operand:<sseintvecmode> 3 "<round_saeonly_nimm_scalar_predicate>"
> "<round_saeonly_constraint>")
> (match_operand:SI 4 "const_0_to_255_operand")]
> UNSPEC_FIXUPIMM)
> (match_dup 2)
The is refined pattern, original pattern has match_dup 1 here.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/101248] [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest.
2021-06-29 2:09 [Bug target/101248] New: [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest crazylht at gmail dot com
2021-06-29 2:12 ` [Bug target/101248] " crazylht at gmail dot com
2021-06-29 2:14 ` crazylht at gmail dot com
@ 2021-06-30 1:08 ` cvs-commit at gcc dot gnu.org
2021-06-30 1:14 ` crazylht at gmail dot com
3 siblings, 0 replies; 5+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2021-06-30 1:08 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101248
--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:
https://gcc.gnu.org/g:ed392e9db434898eccec81edd85323d21d555fe9
commit r12-1923-ged392e9db434898eccec81edd85323d21d555fe9
Author: liuhongt <hongtao.liu@intel.com>
Date: Mon Jun 28 19:27:23 2021 +0800
The upper bits of FIXUPIMMS{S,D} should come from src1 not dest.
gcc/ChangeLog:
PR target/101248
* config/i386/sse.md
(avx512f_sfixupimm<mode><sd_maskz_name><round_saeonly_name>):
Refined to ..
(avx512f_sfixupimm<mode><maskz_scalar_name><round_saeonly_name>):
this.
(avx512f_sfixupimm<mode>_mask<round_saeonly_name>"): Refined.
* config/i386/subst.md (maskz_scalar): New define_subst.
(maskz_scalar_name): New subst_attr.
(maskz_scalar_op5): Ditto.
(round_saeonly_maskz_scalar_op5): Ditto.
(round_saeonly_maskz_scalar_operand5): Ditto.
gcc/testsuite/ChangeLog
PR target/101248
* gcc.target/i386/pr101248.c: New test.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/101248] [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest.
2021-06-29 2:09 [Bug target/101248] New: [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest crazylht at gmail dot com
` (2 preceding siblings ...)
2021-06-30 1:08 ` cvs-commit at gcc dot gnu.org
@ 2021-06-30 1:14 ` crazylht at gmail dot com
3 siblings, 0 replies; 5+ messages in thread
From: crazylht at gmail dot com @ 2021-06-30 1:14 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101248
Hongtao.liu <crazylht at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|UNCONFIRMED |RESOLVED
--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> ---
Fixed in GCC12.
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-06-29 2:09 [Bug target/101248] New: [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest crazylht at gmail dot com
2021-06-29 2:12 ` [Bug target/101248] " crazylht at gmail dot com
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