[Bug target/101882] New: modulus with input and output set to a hard register

[Bug target/101882] New: modulus with input and output set to a hard register

[willschm at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

            Bug ID: 101882
           Summary: modulus with input and output set to a hard register
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: willschm at gcc dot gnu.org
  Target Milestone: ---

Noted on powerpc using recent GCC.
  gcc version 12.0.0 20210812 (experimental) (GCC) 


foofoo9.c:
  register a __asm__("r20");
  b() { a = a % 9 ; }

# does not occur with -O0, or with -mcpu=power8.
$ gcc  -O -mcpu=power9 foofoo9.c 

foofoo9.c: In function ‘b’:
foofoo9.c:2:19: error: unable to generate reloads for impossible constraints:
    2 | b() { a = a % 9 ; }
      |                   ^
(insn 7 9 12 2 (set (reg/v:SI 20 20 [ a ])
        (mod:SI (reg/v:SI 20 20 [ a ])
            (reg:SI 120))) "foofoo9.c":2:13 183 {*modsi3}
     (expr_list:REG_DEAD (reg:SI 120)
        (nil)))
during RTL pass: reload
foofoo9.c:2:19: internal compiler error: in process_alt_operands, at
lra-constraints.c:3108
0x101d9597 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/willschm/gcc/gcc-baseline/gcc/rtl-error.c:108
0x10912b4f process_alt_operands
        /home/willschm/gcc/gcc-baseline/gcc/lra-constraints.c:3108
0x10912b4f curr_insn_transform
        /home/willschm/gcc/gcc-baseline/gcc/lra-constraints.c:4102
0x10916dbb lra_constraints(bool)
        /home/willschm/gcc/gcc-baseline/gcc/lra-constraints.c:5168
0x108fc46f lra(_IO_FILE*)
        /home/willschm/gcc/gcc-baseline/gcc/lra.c:2336
0x1089be8b do_reload
        /home/willschm/gcc/gcc-baseline/gcc/ira.c:5932
0x1089be8b execute
        /home/willschm/gcc/gcc-baseline/gcc/ira.c:6118
Please submit a full bug report,

[Bug target/101882] modulus with input and output set to a hard register

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

Segher Boessenkool <segher at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2021-08-12
           Assignee|unassigned at gcc dot gnu.org      |segher at gcc dot gnu.org
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1

--- Comment #1 from Segher Boessenkool <segher at gcc dot gnu.org> ---
Confirmed.  I'll take it.

[Bug target/101882] modulus with input and output set to a hard register

[mpolacek at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

Marek Polacek <mpolacek at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |ASSIGNED
                 CC|                            |mpolacek at gcc dot gnu.org

--- Comment #2 from Marek Polacek <mpolacek at gcc dot gnu.org> ---
Assignee present -> ASSIGNED.

[Bug target/101882] modulus with input and output set to a hard register

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

--- Comment #3 from Segher Boessenkool <segher at gcc dot gnu.org> ---
(In reply to Marek Polacek from comment #2)
> Assignee present -> ASSIGNED.

Hrm, this used to work automatically when you press "take"?  What changed?

[Bug target/101882] [9/10/11/12 Regression] modulus with input and output set to a hard register

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|modulus with input and      |[9/10/11/12 Regression]
                   |output set to a hard        |modulus with input and
                   |register                    |output set to a hard
                   |                            |register
                 CC|                            |jakub at gcc dot gnu.org
   Target Milestone|---                         |9.5

--- Comment #4 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Started with r9-3950-g2f0b80c7a4ab4254f57ba63de26ebb7896e3742d
Does the modsw instruction really need the early-clobber (i.e. does it first
overwrite the result register before reading the input registers)?
Though, even if it doesn't and this particular issue would be fixed by dropping
it, there can be other instructions that really do need the early-clobber.
Before the r9-3950 change, gcc would silently reload the input from r20 to some
other register to honor the early-clobber.
If that is a behavior that is fine for insns other than inline-asm, perhaps the
r9-3950 changes should be done only when reloading inline-asm and nothing else?

[Bug target/101882] [9/10/11/12 Regression] modulus with input and output set to a hard register

[segher at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

--- Comment #5 from Segher Boessenkool <segher at gcc dot gnu.org> ---
(In reply to Jakub Jelinek from comment #4)
> Started with r9-3950-g2f0b80c7a4ab4254f57ba63de26ebb7896e3742d
> Does the modsw instruction really need the early-clobber (i.e. does it first
> overwrite the result register before reading the input registers)?

No.  And I have a patch, but testing showed some (perhaps unrelated) problems
so it is delayed.

> Though, even if it doesn't and this particular issue would be fixed by
> dropping it, there can be other instructions that really do need the
> early-clobber.

The peephole won't match if an input and output reg are identical, that is
all.  But the peephole very often does not match anyway.

So (in addition to removing the earlyclobber) I did a define_insn_and_split
instead of the peephole.  That is much more reliable.

> Before the r9-3950 change, gcc would silently reload the input from r20 to
> some other register to honor the early-clobber.
> If that is a behavior that is fine for insns other than inline-asm, perhaps
> the
> r9-3950 changes should be done only when reloading inline-asm and nothing
> else?

The LRA change is correct AFAICS.  But combine makes a change that violates
the earlyclobber...  I need to do something about that, too.

[Bug target/101882] [9/10/11/12 Regression] modulus with input and output set to a hard register

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P2

[Bug target/101882] [9/10/11/12/13 Regression] modulus with input and output set to a hard register

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

--- Comment #6 from Peter Bergner <bergner at gcc dot gnu.org> ---
Is there any new status on this?  Fixed perhaps?

[Bug target/101882] [10/11/12/13 Regression] modulus with input and output set to a hard register

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|9.5                         |10.4

--- Comment #7 from Richard Biener <rguenth at gcc dot gnu.org> ---
GCC 9 branch is being closed

[Bug target/101882] [10/11/12/13 Regression] modulus with input and output set to a hard register

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|10.4                        |10.5

--- Comment #8 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
GCC 10.4 is being released, retargeting bugs to GCC 10.5.

[Bug target/101882] [11/12/13/14 Regression] modulus with input and output set to a hard register

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101882

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|10.5                        |11.5

--- Comment #9 from Richard Biener <rguenth at gcc dot gnu.org> ---
GCC 10 branch is being closed.