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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/108185] [RISC-V] Sub-optimal code-gen for vsetvli: redundant stack store Date: Thu, 23 Mar 2023 08:40:48 +0000 [thread overview] Message-ID: <bug-108185-4-T2jLL8kYhQ@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-108185-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185 --- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>: https://gcc.gnu.org/g:3a982e07d28a46da81ee5b65b03a896d84b32a48 commit r13-6826-g3a982e07d28a46da81ee5b65b03a896d84b32a48 Author: Pan Li <pan2.li@intel.com> Date: Wed Mar 8 15:33:33 2023 +0800 RISC-V: Bugfix for rvv bool mode size adjustment Fix the bug of the rvv bool mode size by the adjustment. Besides the mode precision (aka bit size [1, 2, 4, 8, 16, 32, 64]) of the vbool*_t, the mode size (aka byte size) will be adjusted to [1, 1, 1, 1, 2, 4, 8] according to the rvv spec 1.0 isa. The adjustment will provide correct information for the underlying redundant instruction elimiation. Given the below sample code: { vbool1_t v1 = *(vbool1_t*)in; vbool64_t v2 = *(vbool64_t*)in; *(vbool1_t*)(out + 100) = v1; *(vbool64_t*)(out + 200) = v2; } Before the size adjustment: csrr t0,vlenb slli t1,t0,1 csrr a3,vlenb sub sp,sp,t1 slli a4,a3,1 add a4,a4,sp addi a2,a1,100 vsetvli a5,zero,e8,m8,ta,ma sub a3,a4,a3 vlm.v v24,0(a0) vsm.v v24,0(a2) vsm.v v24,0(a3) addi a1,a1,200 csrr t0,vlenb vsetvli a4,zero,e8,mf8,ta,ma slli t1,t0,1 vlm.v v24,0(a3) vsm.v v24,0(a1) add sp,sp,t1 jr ra After the size adjustment: addi a3,a1,100 vsetvli a4,zero,e8,m8,ta,ma addi a1,a1,200 vlm.v v24,0(a0) vsm.v v24,0(a3) vsetvli a5,zero,e8,mf8,ta,ma vlm.v v24,0(a0) vsm.v v24,0(a1) ret Additionally, the size adjust cannot cover all possible combinations of the vbool*_t code pattern like above. We will take a look into it in another patches. PR 108185 PR 108654 gcc/ChangeLog: PR target/108654 PR target/108185 * config/riscv/riscv-modes.def (ADJUST_BYTESIZE): Adjust size for vector mask modes. * config/riscv/riscv.cc (riscv_v_adjust_bytesize): New. * config/riscv/riscv.h (riscv_v_adjust_bytesize): New. gcc/testsuite/ChangeLog: PR target/108654 PR target/108185 * gcc.target/riscv/rvv/base/pr108185-1.c: Update. * gcc.target/riscv/rvv/base/pr108185-2.c: Ditto. * gcc.target/riscv/rvv/base/pr108185-3.c: Ditto. Signed-off-by: Pan Li <pan2.li@intel.com> Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
prev parent reply other threads:[~2023-03-23 8:40 UTC|newest] Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-12-20 3:55 [Bug target/108185] New: [RISC-V]RVV assemble not set vsetvli correct jiawei at iscas dot ac.cn 2022-12-20 3:58 ` [Bug target/108185] " jiawei at iscas dot ac.cn 2022-12-29 9:51 ` kito at gcc dot gnu.org 2023-01-03 1:54 ` jiawei at iscas dot ac.cn 2023-01-03 2:32 ` [Bug target/108185] [RISC-V] Sub-optimal code-gen for vsetvli: redundant stack store kito at gcc dot gnu.org 2023-02-03 3:05 ` juzhe.zhong at rivai dot ai 2023-03-07 13:45 ` cvs-commit at gcc dot gnu.org 2023-03-08 1:11 ` kito at gcc dot gnu.org 2023-03-23 8:40 ` cvs-commit at gcc dot gnu.org [this message]
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