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From: "jiawei at iscas dot ac.cn" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/108185] New: [RISC-V]RVV assemble not set vsetvli correct.
Date: Tue, 20 Dec 2022 03:55:15 +0000 [thread overview]
Message-ID: <bug-108185-4@http.gcc.gnu.org/bugzilla/> (raw)
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185
Bug ID: 108185
Summary: [RISC-V]RVV assemble not set vsetvli correct.
Product: gcc
Version: 13.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: jiawei at iscas dot ac.cn
Target Milestone: ---
Currently, when use gcc13 to compile follow code with rvv
extension(-march=rv64gcv -O3),
void foo5_3 (int32_t * restrict in, int32_t * restrict out, size_t n, int
cond)
{
vint8m1_t v = *(vint8m1_t*)in;
*(vint8m1_t*)out = v;
vbool8_t v3 = *(vbool8_t*)in;
*(vbool8_t*)(out + 200) = v3;
}
it will generate asm as:
vl1re8.v v25,0(a0)
sub a5,a3,a5
vs1r.v v25,0(a1)
vs1r.v v25,0(a5)
seems not use vsetvli correctly, any suggestions?
next reply other threads:[~2022-12-20 3:55 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-20 3:55 jiawei at iscas dot ac.cn [this message]
2022-12-20 3:58 ` [Bug target/108185] " jiawei at iscas dot ac.cn
2022-12-29 9:51 ` kito at gcc dot gnu.org
2023-01-03 1:54 ` jiawei at iscas dot ac.cn
2023-01-03 2:32 ` [Bug target/108185] [RISC-V] Sub-optimal code-gen for vsetvli: redundant stack store kito at gcc dot gnu.org
2023-02-03 3:05 ` juzhe.zhong at rivai dot ai
2023-03-07 13:45 ` cvs-commit at gcc dot gnu.org
2023-03-08 1:11 ` kito at gcc dot gnu.org
2023-03-23 8:40 ` cvs-commit at gcc dot gnu.org
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