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From: "juzhe.zhong at rivai dot ai" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug target/108185] [RISC-V] Sub-optimal code-gen for vsetvli: redundant stack store
Date: Fri, 03 Feb 2023 03:05:42 +0000 [thread overview]
Message-ID: <bug-108185-4-ad86p9gb7s@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-108185-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108185
--- Comment #5 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Revise the testcase, it has a bug here:
void foo5_3 (int32_t * restrict in, int32_t * restrict out, size_t n, int cond)
{
vint8m1_t v = *(vint8m1_t*)in;
*(vint8m1_t*)out = v;
vbool8_t v3 = *(vbool8_t*)in;
*(vbool8_t*)(out + 200) = v3;
vbool16_t v4 = *(vbool16_t *)in;
*(vbool16_t *)(out + 300) = v4;
}
The second vlm.v for vbool16_t is missing which is incorrect codegen.
Confirm for vbool8/16/32/64 all have the same issue.
-fdump-tree-optimized can observe that:
They are all tied and consider as same in GIMPLE IR.
next prev parent reply other threads:[~2023-02-03 3:05 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-20 3:55 [Bug target/108185] New: [RISC-V]RVV assemble not set vsetvli correct jiawei at iscas dot ac.cn
2022-12-20 3:58 ` [Bug target/108185] " jiawei at iscas dot ac.cn
2022-12-29 9:51 ` kito at gcc dot gnu.org
2023-01-03 1:54 ` jiawei at iscas dot ac.cn
2023-01-03 2:32 ` [Bug target/108185] [RISC-V] Sub-optimal code-gen for vsetvli: redundant stack store kito at gcc dot gnu.org
2023-02-03 3:05 ` juzhe.zhong at rivai dot ai [this message]
2023-03-07 13:45 ` cvs-commit at gcc dot gnu.org
2023-03-08 1:11 ` kito at gcc dot gnu.org
2023-03-23 8:40 ` cvs-commit at gcc dot gnu.org
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