[Bug target/108247] New: Missed opportunity to generate shNadd on risc-v

[Bug target/108247] New: Missed opportunity to generate shNadd on risc-v

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108247

            Bug ID: 108247
           Summary: Missed opportunity to generate shNadd on risc-v
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: law at gcc dot gnu.org
                CC: rzinsly at ventanamicro dot com
  Target Milestone: ---
            Target: risc-v

int sub2(int a, long long b) {
  b = (b << 32) >> 31;
  unsigned int x = a + b;
  return x;
}


When compiled with Zba should ideally generate something like this:

  sh1add  a0, a1, a0
  sext.w  a0, a0
  ret


I suspect we need to match something like this as a define_split:

Failed to match this instruction:
(set (reg:SI 142 [ x ])
    (plus:SI (subreg:SI (and:DI (ashift:DI (reg:DI 146)
                    (const_int 1 [0x1]))
                (const_int 4294967294 [0xfffffffe])) 0)
        (subreg:SI (reg:DI 145) 0)))


Or this:


(set (reg:DI 144 [ x ])
    (sign_extend:DI (plus:SI (subreg:SI (and:DI (ashift:DI (reg:DI 146)
                        (const_int 1 [0x1]))
                    (const_int 4294967294 [0xfffffffe])) 0)
            (subreg:SI (reg:DI 145) 0))))

[Bug target/108247] Missed opportunity to generate shNadd on risc-v

[andrew at sifive dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108247

Andrew Waterman <andrew at sifive dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |andrew at sifive dot com

--- Comment #1 from Andrew Waterman <andrew at sifive dot com> ---
The base-ISA-only code sequence has the same instruction count but smaller code
size:

  slli a1, a1, 1
  addw a0, a1, a0
  ret

I guess this example is a proxy for a broader set of missed optimizations, some
of which are actually improved by Zba, so maybe my comment is moot.  But it
would be best not to de-optimize code size in pursuit of opportunities to use
the Zba instructions.

(It also occurs to me that the sh1add + sext.w sequence is easier to fuse
because the instructions have the same destination.  But choosing to increase
code size to avail a fusion opportunity is a uarch-specific tuning decision.)

[Bug target/108247] Missed opportunity to generate shNadd on risc-v

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108247

--- Comment #2 from Jeffrey A. Law <law at gcc dot gnu.org> ---
We shouldn't use Zba just for the sake of using Zba; it needs to be profitable.
 The folks doing the analysis behind this BZ are only looking at instruction
counts -- they're not really thinking about uarch stuff or even code size,
though I think having them look at the latter in addition to dynamic counts
should be possible.

[Bug target/108247] Missed opportunity to generate shNadd on risc-v

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108247

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |INVALID

--- Comment #3 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Per c#1 and c#2.