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* [Bug translation/111416] New: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed @ 2023-09-14 13:17 luke.geeson at cs dot ucl.ac.uk 2023-09-14 16:58 ` [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 " wilco at gcc dot gnu.org ` (3 more replies) 0 siblings, 4 replies; 5+ messages in thread From: luke.geeson at cs dot ucl.ac.uk @ 2023-09-14 13:17 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111416 Bug ID: 111416 Summary: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed Product: gcc Version: 14.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: translation Assignee: unassigned at gcc dot gnu.org Reporter: luke.geeson at cs dot ucl.ac.uk Target Milestone: --- Consider the following litmus test that has buggy behaviour: ``` C test { int64_t x = 0; int64_t y = 0 } P0 (_Atomic int64_t *x, _Atomic int64_t *y) { atomic_fetch_add_explicit(x,1,memory_order_seq_cst); int32_t r0 = atomic_load_explicit(y,memory_order_seq_cst); } void P1 (_Atomic int64_t *x, _Atomic int64_t *y) { atomic_store_explicit(y,1,memory_order_seq_cst); int32_t r0 = atomic_load_explicit(x,memory_order_seq_cst); } exists P0:r0 = 0 /\ P1:r0 = 0 ``` where 'P0:r0 = 0' means thread P0, local variable r0 has value 0 When simulating this test under the C/C++ model from its initial state, the outcome of execution in the exists clause is forbidden by the source model. The allowed outcomes are: ``` { P0:r0=0; P1:r0=1; } { P0:r0=1; P1:r0=0; } { P0:r0=1; P1:r0=1; } ``` When compiling P1, to target armv7-a cortex-a53 (https://godbolt.org/z/efGnsa19G) using clang trunk, compiling the fetch_add on P0 to target a cortex-a53 using clang trunk (`ldaexd;add;stlexd` loop), and the load on P0 to target a cortex-a15 (`ldrd;dmb`) using GCC trunk for cortex-a15. The compiled program has the following outcomes when simulated under the aarch32 model: ``` { P0:r0=0; P1:r0=0; } <--- Forbidden by source model, bug! { P0:r0=0; P1:r0=1; } { P0:r0=1; P1:r0=0; } { P0:r0=1; P1:r0=1; } ``` which is due to the fact the LDRD on P0 can be reordered befofre the stlexd on P0 since there is no dmb barrier to prevent the reordering. Since there is no acquire load on armv7, we propose to fix the bug by adding a fence before the ldrd: ``` dmb ish; ldrd; dmb ish ``` Which prevents the buggy outcome under the aarch32 memory model. I have validated this bug whilst discussing with Wilco from Arm's compiler teams. This bug would not have been caught in normal execution, but only when multiple implementations are mixed together. ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 Implementations are Mixed 2023-09-14 13:17 [Bug translation/111416] New: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed luke.geeson at cs dot ucl.ac.uk @ 2023-09-14 16:58 ` wilco at gcc dot gnu.org 2023-10-31 16:50 ` wilco at gcc dot gnu.org ` (2 subsequent siblings) 3 siblings, 0 replies; 5+ messages in thread From: wilco at gcc dot gnu.org @ 2023-09-14 16:58 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111416 Wilco <wilco at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|UNCONFIRMED |NEW CC| |wilco at gcc dot gnu.org Last reconfirmed| |2023-09-14 Target| |arm-* Ever confirmed|0 |1 Assignee|unassigned at gcc dot gnu.org |wilco at gcc dot gnu.org Component|translation |target --- Comment #1 from Wilco <wilco at gcc dot gnu.org> --- This will be fixed by https://gcc.gnu.org/pipermail/gcc-patches/2023-September/629607.html ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 Implementations are Mixed 2023-09-14 13:17 [Bug translation/111416] New: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed luke.geeson at cs dot ucl.ac.uk 2023-09-14 16:58 ` [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 " wilco at gcc dot gnu.org @ 2023-10-31 16:50 ` wilco at gcc dot gnu.org 2023-10-31 16:51 ` wilco at gcc dot gnu.org 2023-10-31 16:52 ` sjames at gcc dot gnu.org 3 siblings, 0 replies; 5+ messages in thread From: wilco at gcc dot gnu.org @ 2023-10-31 16:50 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111416 Wilco <wilco at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Status|NEW |RESOLVED Resolution|--- |FIXED --- Comment #2 from Wilco <wilco at gcc dot gnu.org> --- Fixed by commit r14-4365-g0731889c026bfe8d55c4851422ca5ec9d037f7a0 #include <stdatomic.h> #include <stdint.h> int64_t f (_Atomic int64_t *p) { return atomic_load (p); } now generates with -O2 -mcpu=cortex-a15: dmb ish ldrd r0, r1, [r0] dmb ish bx lr ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 Implementations are Mixed 2023-09-14 13:17 [Bug translation/111416] New: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed luke.geeson at cs dot ucl.ac.uk 2023-09-14 16:58 ` [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 " wilco at gcc dot gnu.org 2023-10-31 16:50 ` wilco at gcc dot gnu.org @ 2023-10-31 16:51 ` wilco at gcc dot gnu.org 2023-10-31 16:52 ` sjames at gcc dot gnu.org 3 siblings, 0 replies; 5+ messages in thread From: wilco at gcc dot gnu.org @ 2023-10-31 16:51 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111416 Wilco <wilco at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://gcc.gnu.org/bugzill | |a/show_bug.cgi?id=111235 --- Comment #3 from Wilco <wilco at gcc dot gnu.org> --- Fixed by commit r14-4365-g0731889c026bfe8d55c4851422ca5ec9d037f7a0 #include <stdatomic.h> #include <stdint.h> int64_t f (_Atomic int64_t *p) { return atomic_load (p); } now generates with -O2 -mcpu=cortex-a15: dmb ish ldrd r0, r1, [r0] dmb ish bx lr ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 Implementations are Mixed 2023-09-14 13:17 [Bug translation/111416] New: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed luke.geeson at cs dot ucl.ac.uk ` (2 preceding siblings ...) 2023-10-31 16:51 ` wilco at gcc dot gnu.org @ 2023-10-31 16:52 ` sjames at gcc dot gnu.org 3 siblings, 0 replies; 5+ messages in thread From: sjames at gcc dot gnu.org @ 2023-10-31 16:52 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111416 Sam James <sjames at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Target Milestone|--- |14.0 ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2023-10-31 16:52 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-09-14 13:17 [Bug translation/111416] New: [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v7 Implementations are Mixed luke.geeson at cs dot ucl.ac.uk 2023-09-14 16:58 ` [Bug target/111416] [Armv7/v8 Mixing Bug]: 64-bit Sequentially Consistent Load can be Reordered before Store of RMW when v7 and v8 " wilco at gcc dot gnu.org 2023-10-31 16:50 ` wilco at gcc dot gnu.org 2023-10-31 16:51 ` wilco at gcc dot gnu.org 2023-10-31 16:52 ` sjames at gcc dot gnu.org
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