[Bug middle-end/111621] New: [RISC-V] Bad register allocation in vadd.vi may cause operational error

[Bug middle-end/111621] New: [RISC-V] Bad register allocation in vadd.vi may cause operational error

[mumuxi_ll at outlook dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621

            Bug ID: 111621
           Summary: [RISC-V] Bad register allocation in vadd.vi may cause
                    operational error
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: middle-end
          Assignee: unassigned at gcc dot gnu.org
          Reporter: mumuxi_ll at outlook dot com
  Target Milestone: ---

Hi;

My source code can be fond at https://godbolt.org/z/8v9Wxx9Yf.

The porblem is that when compiling with -O2/-O3, vadd.vi will allocate a
different  register for vd compared to vs2, then the actual operation will only
update the first data in vd instead of all. In cases such as -O0, vadd.vi will
allocate the same registers to vd and vs2, and all vd values will be refreshed
after execution.

Thanks!

[Bug middle-end/111621] [RISC-V] Bad register allocation in vadd.vi may cause operational error

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Created attachment 56012
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56012&action=edit
testcase (-march=rv64imafdcv -mabi=lp64d -O3)

Please next time attach the testcase (or put it inline) and not just a link to
godbolt. Also add the full version of GCC which you can get via the `-v`
option.

[Bug middle-end/111621] [RISC-V] Bad register allocation in vadd.vi may cause operational error

[mumuxi_ll at outlook dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621

--- Comment #2 from liu xu <mumuxi_ll at outlook dot com> ---
I'm sorry about that and will notice that next time.

The toolchain I used was built using the gcc master branch, and another point
that needs to be added is that only the vadd.vi instruction with mask will
encounter the above problem, and without mask, it will not.

Looking forward to your reply！

[Bug middle-end/111621] [RISC-V] Bad register allocation in vadd.vi may cause operational error

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111621

JuzheZhong <juzhe.zhong at rivai dot ai> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |juzhe.zhong at rivai dot ai

--- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
I don't think this is a bug.

You are using  __riscv_vadd_vx_i32m4_m.

The vd is not necessary same as vs2 and this intrinsic is supposed to use
TAMA which means that the tailed element and mask-inactive elements are
agnostic (can be either all ones or original value).

So the codegen is correct even though -O0 result is different from -O2/-O3.

If you want to use make vd same as vs2, you should use these following
intrinsics:

__riscv_vadd_vx_i32m4_tu
__riscv_vadd_vx_i32m4_mu
__riscv_vadd_vx_i32m4_tumu