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* [Bug middle-end/111743] New: shifts in bit field accesses don't combine with other shifts @ 2023-10-09 18:57 andi-gcc at firstfloor dot org 2023-10-09 19:09 ` [Bug middle-end/111743] " pinskia at gcc dot gnu.org ` (5 more replies) 0 siblings, 6 replies; 7+ messages in thread From: andi-gcc at firstfloor dot org @ 2023-10-09 18:57 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743 Bug ID: 111743 Summary: shifts in bit field accesses don't combine with other shifts Product: gcc Version: 13.1.0 Status: UNCONFIRMED Severity: normal Priority: P3 Component: middle-end Assignee: unassigned at gcc dot gnu.org Reporter: andi-gcc at firstfloor dot org Target Milestone: --- (not sure it's the middle-end, picked arbitrarily) The following code struct bf { unsigned a : 10, b : 20, c : 10; }; unsigned fbc(struct bf bf) { return bf.b | (bf.c << 20); } generates: movq %rdi, %rax shrq $10, %rdi shrq $32, %rax andl $1048575, %edi andl $1023, %eax sall $20, %eax orl %edi, %eax ret It doesn't understand that the shift right can be combined with the shift left. Also not sure why the shift left is arithmetic (this should be all unsigned) clang does the simplification which ends up one instruction shorter: movl %edi, %eax shrl $10, %eax andl $1048575, %eax # imm = 0xFFFFF shrq $12, %rdi andl $1072693248, %edi # imm = 0x3FF00000 orl %edi, %eax retq ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts 2023-10-09 18:57 [Bug middle-end/111743] New: shifts in bit field accesses don't combine with other shifts andi-gcc at firstfloor dot org @ 2023-10-09 19:09 ` pinskia at gcc dot gnu.org 2023-10-09 19:19 ` andi-gcc at firstfloor dot org ` (4 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: pinskia at gcc dot gnu.org @ 2023-10-09 19:09 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743 --- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> --- Remember types smaller than int is prompted to int . ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts 2023-10-09 18:57 [Bug middle-end/111743] New: shifts in bit field accesses don't combine with other shifts andi-gcc at firstfloor dot org 2023-10-09 19:09 ` [Bug middle-end/111743] " pinskia at gcc dot gnu.org @ 2023-10-09 19:19 ` andi-gcc at firstfloor dot org 2023-10-09 20:40 ` pinskia at gcc dot gnu.org ` (3 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: andi-gcc at firstfloor dot org @ 2023-10-09 19:19 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743 --- Comment #2 from Andi Kleen <andi-gcc at firstfloor dot org> --- Okay then it doesn't understand that SHL_signed and SHR_unsigned can be combined when one the values came from a shorter unsigned. ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts 2023-10-09 18:57 [Bug middle-end/111743] New: shifts in bit field accesses don't combine with other shifts andi-gcc at firstfloor dot org 2023-10-09 19:09 ` [Bug middle-end/111743] " pinskia at gcc dot gnu.org 2023-10-09 19:19 ` andi-gcc at firstfloor dot org @ 2023-10-09 20:40 ` pinskia at gcc dot gnu.org 2023-10-09 20:46 ` pinskia at gcc dot gnu.org ` (2 subsequent siblings) 5 siblings, 0 replies; 7+ messages in thread From: pinskia at gcc dot gnu.org @ 2023-10-09 20:40 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743 Andrew Pinski <pinskia at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- Ever confirmed|0 |1 CC| |pinskia at gcc dot gnu.org Severity|normal |enhancement Last reconfirmed| |2023-10-09 Status|UNCONFIRMED |NEW --- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> --- RTL wise we have: Trying 6, 8 -> 9: 6: {r108:DI=r105:DI 0>>0x20;clobber flags:CC;} REG_UNUSED flags:CC 8: {r110:SI=r108:DI#0&0x3ff;clobber flags:CC;} REG_UNUSED flags:CC REG_DEAD r108:DI 9: {r111:SI=r110:SI<<0x14;clobber flags:CC;} REG_DEAD r110:SI REG_UNUSED flags:CC Failed to match this instruction: (parallel [ (set (reg:SI 111) (and:SI (ashift:SI (subreg:SI (zero_extract:DI (reg/v:DI 105 [ bf ]) (const_int 32 [0x20]) (const_int 32 [0x20])) 0) (const_int 20 [0x14])) (const_int 1072693248 [0x3ff00000]))) (clobber (reg:CC 17 flags)) ]) This should have been simplified. Anyways bitfields have issues even on the gimple level as they are not lowered until expand ... ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts 2023-10-09 18:57 [Bug middle-end/111743] New: shifts in bit field accesses don't combine with other shifts andi-gcc at firstfloor dot org ` (2 preceding siblings ...) 2023-10-09 20:40 ` pinskia at gcc dot gnu.org @ 2023-10-09 20:46 ` pinskia at gcc dot gnu.org 2023-10-10 0:32 ` andi-gcc at firstfloor dot org 2023-10-10 0:40 ` pinskia at gcc dot gnu.org 5 siblings, 0 replies; 7+ messages in thread From: pinskia at gcc dot gnu.org @ 2023-10-09 20:46 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743 Andrew Pinski <pinskia at gcc dot gnu.org> changed: What |Removed |Added ---------------------------------------------------------------------------- See Also| |https://gcc.gnu.org/bugzill | |a/show_bug.cgi?id=107601 --- Comment #4 from Andrew Pinski <pinskia at gcc dot gnu.org> --- x86_64 defines SLOW_BYTE_ACCESS which caues some (if not all) of the issues here: ``` ;; _3 = bf.c; (insn 9 8 10 (parallel [ (set (reg:DI 106) (lshiftrt:DI (reg/v:DI 104 [ bf ]) (const_int 32 [0x20]))) (clobber (reg:CC 17 flags)) ]) "/app/example.cpp":5:58 -1 (nil)) (insn 10 9 0 (parallel [ (set (reg:HI 100 [ _3 ]) (and:HI (subreg:HI (reg:DI 106) 0) (const_int 1023 [0x3ff]))) (clobber (reg:CC 17 flags)) ]) "/app/example.cpp":5:58 -1 (nil)) ;; _4 = (unsigned int) _3; (insn 11 10 0 (set (reg:SI 101 [ _4 ]) (zero_extend:SI (reg:HI 100 [ _3 ]))) "/app/example.cpp":5:46 -1 (nil)) ``` Uses HImode (short) here due to SLOW_BYTE_ACCESS being defined rather than the SImode (int). ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts 2023-10-09 18:57 [Bug middle-end/111743] New: shifts in bit field accesses don't combine with other shifts andi-gcc at firstfloor dot org ` (3 preceding siblings ...) 2023-10-09 20:46 ` pinskia at gcc dot gnu.org @ 2023-10-10 0:32 ` andi-gcc at firstfloor dot org 2023-10-10 0:40 ` pinskia at gcc dot gnu.org 5 siblings, 0 replies; 7+ messages in thread From: andi-gcc at firstfloor dot org @ 2023-10-10 0:32 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743 --- Comment #5 from Andi Kleen <andi-gcc at firstfloor dot org> --- config/i386/i386.h:#define SLOW_BYTE_ACCESS 0 You mean it doesn't define it? ^ permalink raw reply [flat|nested] 7+ messages in thread
* [Bug middle-end/111743] shifts in bit field accesses don't combine with other shifts 2023-10-09 18:57 [Bug middle-end/111743] New: shifts in bit field accesses don't combine with other shifts andi-gcc at firstfloor dot org ` (4 preceding siblings ...) 2023-10-10 0:32 ` andi-gcc at firstfloor dot org @ 2023-10-10 0:40 ` pinskia at gcc dot gnu.org 5 siblings, 0 replies; 7+ messages in thread From: pinskia at gcc dot gnu.org @ 2023-10-10 0:40 UTC (permalink / raw) To: gcc-bugs https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111743 --- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> --- (In reply to Andi Kleen from comment #5) > config/i386/i386.h:#define SLOW_BYTE_ACCESS 0 > > You mean it doesn't define it? The default is 1. Anyways in this case I was wrong but defining it to 0 causes other issues. ^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-10-10 0:40 UTC | newest] Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2023-10-09 18:57 [Bug middle-end/111743] New: shifts in bit field accesses don't combine with other shifts andi-gcc at firstfloor dot org 2023-10-09 19:09 ` [Bug middle-end/111743] " pinskia at gcc dot gnu.org 2023-10-09 19:19 ` andi-gcc at firstfloor dot org 2023-10-09 20:40 ` pinskia at gcc dot gnu.org 2023-10-09 20:46 ` pinskia at gcc dot gnu.org 2023-10-10 0:32 ` andi-gcc at firstfloor dot org 2023-10-10 0:40 ` pinskia at gcc dot gnu.org
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