[Bug c/111765] New: RISC-V: Faild to vectorize gen-vect-34.c

[Bug c/111765] New: RISC-V: Faild to vectorize gen-vect-34.c

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111765

            Bug ID: 111765
           Summary: RISC-V: Faild to vectorize gen-vect-34.c
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

https://godbolt.org/z/17qYYKWPM

float summul(int n, float *arg1, float *arg2)
{                                                  
    int i;                                             
    float res1 = 1.0;
    for(i = 0; i < n; i++) {
      if(arg2[i]) 
        res1 *= arg1[i];
    }                                                  
    return res1;                                       
}

I found both ARM SVE and RVV failed to vectorize this case wheras X86 can
vectorize it with -mavx2.

It seems that we need some tricks on both SVE and RVV backend ?

[Bug tree-optimization/111765] RISC-V: Faild to vectorize gen-vect-34.c

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111765

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
For SVE:
/app/example.cpp:6:18: missed:   missing target support for reduction on
variable-length vectors.

I assume it is the same issue for RVV.

[Bug tree-optimization/111765] RISC-V: Faild to vectorize gen-vect-34.c

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111765

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
(In reply to Andrew Pinski from comment #1)
> For SVE:
> /app/example.cpp:6:18: missed:   missing target support for reduction on
> variable-length vectors.
> 
> I assume it is the same issue for RVV.

Yeah.

So may be we should adjust the dump check:

/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { target
vect_masked_load && !vect_variable_length } } } */

?

[Bug tree-optimization/111765] RISC-V: Faild to vectorize gen-vect-34.c

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=111765

--- Comment #3 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
If we specify the vector length to RVV and SVE:

https://godbolt.org/z/njvsqYWhn

Both can vectorize.

ARM SVE: -msve-vector-bits=128

RVV: --param=riscv-autovec-preference=fixed-vlmax