[Bug target/113001] New: [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[Bug target/113001] New: [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001

            Bug ID: 113001
           Summary: [14 Regression] RISCV Zicond ICE: in extract_insn, at
                    recog.cc:2812 with -O2 rv64gcv_zicond
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: patrick at rivosinc dot com
  Target Milestone: ---

Created attachment 56872
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=56872&action=edit
-freport-bug output

> /scratch/tc-testing/tc-dec-13-trunk/build-rv64gcv/bin/riscv64-unknown-linux-gnu-gcc -march=rv64gc_zicond -mabi=lp64d -O2 red.c -freport-bug
red.c: In function 'g':
red.c:11:1: error: unrecognizable insn:
   11 | }
      | ^
(insn 14 13 15 4 (set (reg:DI 145)
        (if_then_else:DI (ne:DI (reg:DI 138 [ _7 ])
                (const_int 0 [0]))
            (reg:DI 138 [ _7 ])
            (reg:DI 146))) -1
     (nil))
during RTL pass: vregs
red.c:11:1: internal compiler error: in extract_insn, at recog.cc:2812
0xa2a515 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        ../../../gcc/gcc/rtl-error.cc:108
0xa2a537 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        ../../../gcc/gcc/rtl-error.cc:116
0xa28e0b extract_insn(rtx_insn*)
        ../../../gcc/gcc/recog.cc:2812
0xedee3e instantiate_virtual_regs_in_insn
        ../../../gcc/gcc/function.cc:1611
0xedee3e instantiate_virtual_regs
        ../../../gcc/gcc/function.cc:1994
0xedee3e execute
        ../../../gcc/gcc/function.cc:2041
Please submit a full bug report, with preprocessed source.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.
Preprocessed source stored into /scratch/tmp/ccw1t5xI.out file, please attach
this to your bugreport.

Testcase:
long a, b;
int c, d;
void e(long *f) {
  (b = *f) && --b;
  for (; c;)
    ;
}
void g() {
  for (; d; d--)
    e(&a);
}

Godbolt: https://godbolt.org/z/s6hqh6eo8

-freport bug output is attached.

pr112871 looks related but is on rv32gc_zicond.

[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001

--- Comment #1 from Patrick O'Neill <patrick at rivosinc dot com> ---
Bisected to r14-3041-g18c453f0e63

[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |14.0

[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |pinskia at gcc dot gnu.org
   Last reconfirmed|                            |2024-02-22
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Confirmed.

[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P4

[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001

--- Comment #3 from Jeffrey A. Law <law at gcc dot gnu.org> ---
*** Bug 112871 has been marked as a duplicate of this bug. ***

[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jeff Law <law@gcc.gnu.org>:

https://gcc.gnu.org/g:10cbfcd60f9e5bdbe486e1c0192e0f168d899b77

commit r14-9341-g10cbfcd60f9e5bdbe486e1c0192e0f168d899b77
Author: Jeff Law <jlaw@ventanamicro.com>
Date:   Wed Mar 6 09:50:44 2024 -0700

    [PR target/113001] Fix incorrect operand swapping in conditional move

    This bug totally fell off my radar.  Sorry about that.

    We have some special casing the conditional move expander to simplify a
    conditional move when comparing a register against zero and that same
register
    is one of the arms.

    Specifically a (eq (reg) (const_int 0)) where reg is also the true arm or
(ne
    (reg) (const_int 0)) where reg is the false arm need not use the fully
    generalized conditional move, thus saving an instruction for those cases.

    In the NE case we swapped the operands, but didn't swap the condition,
which
    led to the ICE due to an unrecognized pattern.  THe backend actually has
    distinct patterns for those two cases.  So swapping the operands is neither
    needed nor advisable.

    Regression tested on rv64gc and verified the new tests pass.

    Pushing to the trunk.

            PR target/113001
            PR target/112871
    gcc/
            * config/riscv/riscv.cc (expand_conditional_move): Do not swap
            operands when the comparison operand is the same as the false
            arm for a NE test.

    gcc/testsuite
            * gcc.target/riscv/zicond-ice-3.c: New test.
            * gcc.target/riscv/zicond-ice-4.c: New test.

[Bug target/113001] [14 Regression] RISCV Zicond ICE: in extract_insn, at recog.cc:2812 with -O2 rv64gcv_zicond

[law at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=113001

Jeffrey A. Law <law at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|NEW                         |RESOLVED

--- Comment #5 from Jeffrey A. Law <law at gcc dot gnu.org> ---
Fixed on the trunk.