[Bug c/114988] New: RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2

[Bug c/114988] New: RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114988

            Bug ID: 114988
           Summary: RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2
           Product: gcc
           Version: 14.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: juzhe.zhong at rivai dot ai
  Target Milestone: ---

https://godbolt.org/z/ncxrx3fK9

#include <stdint.h>
#include <riscv_vector.h>

vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t vl)
{
  return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl);
}

with -march=rv64gcv -O3:

<source>:6:1: error: unrecognizable insn:
    6 | }
      | ^
(insn 8 5 12 2 (set (reg:RVVMF2SF 134 [ <retval> ])
        (if_then_else:RVVMF2SF (unspec:RVVMF64BI [
                    (const_vector:RVVMF64BI repeat [
                            (const_int 1 [0x1])
                        ])
                    (reg/v:DI 137 [ vl ])
                    (const_int 2 [0x2]) repeated x2
                    (const_int 0 [0])
                    (const_int 7 [0x7])
                    (reg:SI 66 vl)
                    (reg:SI 67 vtype)
                    (reg:SI 69 frm)
                ] UNSPEC_VPREDICATE)
            (minus:RVVMF2SF (reg/v:RVVMF2SF 135 [ vs2 ])
                (float_extend:RVVMF2SF (vec_duplicate:RVVMF4HF (reg/v:HF 136 [
rs1 ]))))
            (unspec:RVVMF2SF [
                    (reg:DI 0 zero)
                ] UNSPEC_VUNDEF))) "<source>":5:10 -1
     (nil))

FP16 vector need zvfh, so such intrinsic should be reported as illegal
intrinsic in frontend instead of an ICE.

with -rv64gcv_zvfh:
It can be compiled:

        vsetvli zero,a0,e16,mf4,ta,ma
        vfwsub.wf       v8,v8,fa0
        ret

[Bug c/114988] RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114988

--- Comment #1 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Ideally, it should be reported as (-march=rv64gc):

https://godbolt.org/z/3P76YEb9s


<source>: In function 'test_vfwsub_wf_f32mf2':
<source>:4:15: error: return type 'vfloat32mf2_t' requires the V ISA extension
    4 | vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1,
size_t vl) {
      |               ^~~~~~~~~~~~~~~~~~~~~
Compiler returned: 1

[Bug target/114988] RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2

[juzhe.zhong at rivai dot ai]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114988

--- Comment #2 from JuzheZhong <juzhe.zhong at rivai dot ai> ---
Li Pan is going to work on it.

Hi, kito and Jeff.

Can this fix backport to GCC-14 ?

[Bug target/114988] RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114988

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |kito at gcc dot gnu.org

--- Comment #3 from Kito Cheng <kito at gcc dot gnu.org> ---
> Can this fix backport to GCC-14 ?

Sure, GCC 14.1 released, so it open to accept fixes now :)

[Bug target/114988] RISC-V: ICE in intrinsic __riscv_vfwsub_wf_f32mf2

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=114988

--- Comment #4 from GCC Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Pan Li <panli@gcc.gnu.org>:

https://gcc.gnu.org/g:41b3cf262e61aee9d26380f1c820e0eaae740f50

commit r15-435-g41b3cf262e61aee9d26380f1c820e0eaae740f50
Author: Pan Li <pan2.li@intel.com>
Date:   Sat May 11 15:25:28 2024 +0800

    RISC-V: Bugfix ICE for RVV intrinisc vfw on _Float16 scalar

    For the vfw vx format RVV intrinsic, the scalar type _Float16 also
    requires the zvfh extension.  Unfortunately,  we only check the
    vector tree type and miss the scalar _Float16 type checking.  For
    example:

    vfloat32mf2_t test_vfwsub_wf_f32mf2(vfloat32mf2_t vs2, _Float16 rs1, size_t
vl)
    {
      return __riscv_vfwsub_wf_f32mf2(vs2, rs1, vl);
    }

    It should report some error message like zvfh extension is required
    instead of ICE for unreg insn.

    This patch would like to make up such kind of validation for _Float16
    in the RVV intrinsic API.  It will report some error like below when
    there is no zvfh enabled.

    error: built-in function '__riscv_vfwsub_wf_f32mf2(vs2,  rs1,  vl)'
      requires the zvfhmin or zvfh ISA extension

    Passed the rv64gcv fully regression tests, included c/c++/fortran.

            PR target/114988

    gcc/ChangeLog:

            * config/riscv/riscv-vector-builtins.cc
            (validate_instance_type_required_extensions): New func impl to
            validate the intrinisc func type ops.
            (expand_builtin): Validate instance type before expand.

    gcc/testsuite/ChangeLog:

            * gcc.target/riscv/rvv/base/pr114988-1.c: New test.
            * gcc.target/riscv/rvv/base/pr114988-2.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>