[Bug target/99271] New: [10/11 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

[Bug target/99271] New: [10/11 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271

            Bug ID: 99271
           Summary: [10/11 regression] Wrong code for Arm-v8-m.main CMSE
                    calling __gnu_cmse_nonsecure_call
           Product: gcc
           Version: 10.0
            Status: UNCONFIRMED
          Keywords: wrong-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: rearnsha at gcc dot gnu.org
  Target Milestone: ---
            Target: arm

The code fragment:

typedef void (*f)(int) __attribute__((cmse_nonsecure_call));

void bar(f func, int a)
{
  func(a);
}

When compiled with -O2 -mcmse -march=armv8-m.main -mthumb

Incorrectly optimizes the code sequence so that the register used for the
function pointer is not correctly initialized.  The problem was introduced in
r10-6017, so affects gcc-10 and gcc-11.

Current code:

        mov     r3, r0
        mov     r0, r1
        push    {r4, lr}
        lsrs    r3, r3, #1
        lsls    r3, r3, #1
        mov     r1, r3
        mov     r2, r3
        bl      __gnu_cmse_nonsecure_call  // r4 not initialized above.
        pop     {r4, pc}

Correct code

        push    {r4, lr}
        mov     r4, r0
        mov     r0, r1
        lsrs    r4, r4, #1
        lsls    r4, r4, #1
        mov     r1, r4
        mov     r2, r4
        mov     r3, r4
        bl      __gnu_cmse_nonsecure_call // r4 = function with LSB cleared.
        pop     {r4, pc}

[Bug target/99271] [10/11 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2021-02-25
             Status|UNCONFIRMED                 |NEW
           Priority|P3                          |P1
           Assignee|unassigned at gcc dot gnu.org      |rearnsha at gcc dot gnu.org

[Bug target/99271] [10/11 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Earnshaw <rearnsha@gcc.gnu.org>:

https://gcc.gnu.org/g:44ab1cc1df6ec4ff50210401acdcb26e80343541

commit r11-7400-g44ab1cc1df6ec4ff50210401acdcb26e80343541
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Mon Feb 22 15:00:53 2021 +0000

    arm: force use of r4 for __gnu_cmse_nonsecure_call when !FPCXT [PR99271]

    Commit r10-6017 relaxed the constraint on thumb2 calls to
    __gnu_cmse_nonsecure_call to allow any register for the call address.
    Although the initial code expansion continues to use r4 with the FPCXT
    extension is not enabled, the change was unsafe because subsequent
    optimizations could use the additional freedom to change which
    register was being used.

    To fix this we need to split the output patterns in the machine
    description to use distinct recognizers: one with the additional
    freedom when FPCXT is enabled an another that retains the original
    restrictions when the extension is not available.

    gcc:
            PR target/99271
            * config/arm/thumb2.md (nonsecure_call_reg_thumb2_fpcxt): New
pattern.
            (nonsecure_call_value_reg_thumb2_fpcxt): Likewise.
            (nonsecure_call_reg_thumb2): Restrict to using r4 for the callee
            address and disable when the FPCXT is not available.
            (nonsecure_call_value_reg_thumb2): Likewise.

    gcc/testsuite:
            * gcc.target/arm/cmse/cmse-18.c: New test.

[Bug target/99271] [10 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[10/11 regression] Wrong    |[10 regression] Wrong code
                   |code for Arm-v8-m.main CMSE |for Arm-v8-m.main CMSE
                   |calling                     |calling
                   |__gnu_cmse_nonsecure_call   |__gnu_cmse_nonsecure_call
             Status|NEW                         |ASSIGNED

--- Comment #2 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Fixed on trunk.  Will backport to 10 shortly.

[Bug target/99271] [10 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |10.3

[Bug target/99271] [10 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Richard Earnshaw
<rearnsha@gcc.gnu.org>:

https://gcc.gnu.org/g:1b3bb23a576e6a864f540e3bea5097f47fea507c

commit r10-9398-g1b3bb23a576e6a864f540e3bea5097f47fea507c
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Mon Feb 22 15:00:53 2021 +0000

    arm: force use of r4 for __gnu_cmse_nonsecure_call when !FPCXT [PR99271]

    Commit r10-6017 relaxed the constraint on thumb2 calls to
    __gnu_cmse_nonsecure_call to allow any register for the call address.
    Although the initial code expansion continues to use r4 with the FPCXT
    extension is not enabled, the change was unsafe because subsequent
    optimizations could use the additional freedom to change which
    register was being used.

    To fix this we need to split the output patterns in the machine
    description to use distinct recognizers: one with the additional
    freedom when FPCXT is enabled an another that retains the original
    restrictions when the extension is not available.

    gcc:
            PR target/99271
            * config/arm/thumb2.md (nonsecure_call_reg_thumb2_fpcxt): New
pattern.
            (nonsecure_call_value_reg_thumb2_fpcxt): Likewise.
            (nonsecure_call_reg_thumb2): Restrict to using r4 for the callee
            address and disable when the FPCXT is not available.
            (nonsecure_call_value_reg_thumb2): Likewise.

    gcc/testsuite:
            * gcc.target/arm/cmse/cmse-18.c: New test.

[Bug target/99271] [10 regression] Wrong code for Arm-v8-m.main CMSE calling __gnu_cmse_nonsecure_call

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99271

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|ASSIGNED                    |RESOLVED

--- Comment #4 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Fixed on all affected branches.