[Bug target/99702] New: [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy()

[Bug target/99702] New: [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy()

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

            Bug ID: 99702
           Summary: [11 Regression] ICE: RTL check: expected code
                    'const_int', have 'subreg' in riscv_expand_block_move,
                    at config/riscv/riscv.c:3262 with memcpy()
           Product: gcc
           Version: 11.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: riscv64-unknown-linux-gnu

Created attachment 50444
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50444&action=edit
reduced testcase (from libgcc/unwind-dw2.c)

Compiler output:
$ cc1 -mabi=lp64d -march=rv64imafdc -O testcase.c 
 foo
Analyzing compilation unit
Performing interprocedural optimizations
 <*free_lang_data> {heap 860k} <visibility> {heap 860k} <build_ssa_passes>
{heap 860k} <opt_local_passes> {heap 992k} <remove_symbols> {heap 1720k}
<targetclone> {heap 1720k} <free-fnsummary> {heap 1720k}Streaming LTO
 <whole-program> {heap 1720k} <profile_estimate> {heap 1720k} <fnsummary> {heap
1720k} <inline> {heap 1720k} <pure-const> {heap 1720k} <modref> {heap 1720k}
<free-fnsummary> {heap 1720k} <static-var> {heap 1720k} <single-use> {heap
1720k} <comdats> {heap 1720k}Assembling functions:
 fooduring RTL pass: expand

testcase.c: In function 'foo':
testcase.c:4:3: internal compiler error: RTL check: expected code 'const_int',
have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262
    4 |   __builtin_memcpy(i, j, n);
      |   ^~~~~~~~~~~~~~~~~~~~~~~~~
0x6c4289 rtl_check_failed_code1(rtx_def const*, rtx_code, char const*, int,
char const*)
        /repo/gcc-trunk/gcc/rtl.c:879
0x776ff0 riscv_expand_block_move(rtx_def*, rtx_def*, rtx_def*)
        /repo/gcc-trunk/gcc/config/riscv/riscv.c:3262
0x14c4ba0 gen_cpymemsi(rtx_def*, rtx_def*, rtx_def*, rtx_def*)
        /repo/gcc-trunk/gcc/config/riscv/riscv.md:1528
0xd4b8d8 maybe_expand_insn(insn_code, unsigned int, expand_operand*)
        /repo/gcc-trunk/gcc/optabs.c:7820
0xae7f5e emit_block_move_via_pattern
        /repo/gcc-trunk/gcc/expr.c:1873
0xae7f5e emit_block_move_hints(rtx_def*, rtx_def*, rtx_def*, block_op_methods,
unsigned int, long, unsigned long, unsigned long, unsigned long, bool, bool*,
bool)
        /repo/gcc-trunk/gcc/expr.c:1665
0x977aa3 expand_builtin_memory_copy_args
        /repo/gcc-trunk/gcc/builtins.c:6053
0x989470 expand_builtin_memcpy
        /repo/gcc-trunk/gcc/builtins.c:5906
0x98c3a2 expand_builtin(tree_node*, rtx_def*, rtx_def*, machine_mode, int)
        /repo/gcc-trunk/gcc/builtins.c:9955
0xade284 expand_expr_real_1(tree_node*, rtx_def*, machine_mode,
expand_modifier, rtx_def**, bool)
        /repo/gcc-trunk/gcc/expr.c:11282
0x9b9d5c expand_expr
        /repo/gcc-trunk/gcc/expr.h:282
0x9b9d5c expand_call_stmt
        /repo/gcc-trunk/gcc/cfgexpand.c:2840
0x9b9d5c expand_gimple_stmt_1
        /repo/gcc-trunk/gcc/cfgexpand.c:3844
0x9b9d5c expand_gimple_stmt
        /repo/gcc-trunk/gcc/cfgexpand.c:4008
0x9ba7a9 expand_gimple_basic_block
        /repo/gcc-trunk/gcc/cfgexpand.c:6045
0x9bc4a6 execute
        /repo/gcc-trunk/gcc/cfgexpand.c:6729
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

$ xgcc -v
Using built-in specs.
COLLECT_GCC=/repo/build-gcc-trunk-riscv64/./gcc/xgcc
Target: riscv64-unknown-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl
--with-sysroot=/usr/riscv64-unknown-linux-gnu --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=riscv64-unknown-linux-gnu
--with-ld=/usr/bin/riscv64-unknown-linux-gnu-ld
--with-as=/usr/bin/riscv64-unknown-linux-gnu-as --disable-multilib
--disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r11-7753-20210321172739-gfc24ea23742-checking-yes-rtl-df-extra-riscv64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 11.0.1 20210321 (experimental) (GCC) 

This breaks compiler build with --enable-checking=yes,rtl,df,extra

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy()

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

Zdenek Sojka <zsojka at seznam dot cz> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
      Known to fail|                            |11.0

--- Comment #1 from Zdenek Sojka <zsojka at seznam dot cz> ---
This might be a recent regression, r11-7696 works fine.

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since r11-7757-gfc9c4e5fc50c7fcbd27d6cb3dd372f7da8216954

[marxin at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

Martin Liška <marxin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[11 Regression] ICE: RTL    |[11 Regression] ICE: RTL
                   |check: expected code        |check: expected code
                   |'const_int', have 'subreg'  |'const_int', have 'subreg'
                   |in riscv_expand_block_move, |in riscv_expand_block_move,
                   |at                          |at
                   |config/riscv/riscv.c:3262   |config/riscv/riscv.c:3262
                   |with memcpy()               |with memcpy() since
                   |                            |r11-7757-gfc9c4e5fc50c7fcbd
                   |                            |27d6cb3dd372f7da8216954
             Status|UNCONFIRMED                 |NEW
     Ever confirmed|0                           |1
   Last reconfirmed|                            |2021-03-22
   Target Milestone|---                         |11.0
                 CC|                            |marxin at gcc dot gnu.org,
                   |                            |sinan.lin at aalto dot fi
      Known to work|                            |10.2.0

--- Comment #2 from Martin Liška <marxin at gcc dot gnu.org> ---
Started with r11-7757-gfc9c4e5fc50c7fcbd27d6cb3dd372f7da8216954.

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since r11-7757-gfc9c4e5fc50c7fcbd27d6cb3dd372f7da8216954

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

--- Comment #3 from Zdenek Sojka <zsojka at seznam dot cz> ---
(In reply to Martin Liška from comment #2)
> Started with r11-7757-gfc9c4e5fc50c7fcbd27d6cb3dd372f7da8216954.

Thank you for the analysis! However I don't think that's possible, since I was
observing the failure on r11-7753 ; I even reported this before r11-7757 was
available.

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since r11-7757-gfc9c4e5fc50c7fcbd27d6cb3dd372f7da8216954

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |kito at gcc dot gnu.org
             Status|NEW                         |ASSIGNED

--- Comment #4 from Kito Cheng <kito at gcc dot gnu.org> ---
Hi Zdenek:
Confirmed, and has fix patch, it's trivial fix, so I'll commit the fix after
test.

I believe its cause by this patch:

https://gcc.gnu.org/git/gitweb.cgi?p=gcc.git;h=d9f0ade001533c9544bf2153b6baa8844ec0bee4


Hi Martin:

Thanks for the info :)

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since g:d9f0ade001533c9544bf2153b6baa8844ec0bee4

[marxin at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

Martin Liška <marxin at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
            Summary|[11 Regression] ICE: RTL    |[11 Regression] ICE: RTL
                   |check: expected code        |check: expected code
                   |'const_int', have 'subreg'  |'const_int', have 'subreg'
                   |in riscv_expand_block_move, |in riscv_expand_block_move,
                   |at                          |at
                   |config/riscv/riscv.c:3262   |config/riscv/riscv.c:3262
                   |with memcpy() since         |with memcpy() since
                   |r11-7757-gfc9c4e5fc50c7fcbd |g:d9f0ade001533c9544bf2153b
                   |27d6cb3dd372f7da8216954     |6baa8844ec0bee4

--- Comment #5 from Martin Liška <marxin at gcc dot gnu.org> ---
Yes, sorry, I made a copy&paste error, it's really
g:d9f0ade001533c9544bf2153b6baa8844ec0bee4.

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since g:d9f0ade001533c9544bf2153b6baa8844ec0bee4

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:540dace2ed3949571f2ce6cb007354e69bda0cb2

commit r11-7759-g540dace2ed3949571f2ce6cb007354e69bda0cb2
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Mon Mar 22 16:32:45 2021 +0800

    PR target/99702: Check RTL type before get value

    gcc/ChangeLog:

            PR target/99702
            * config/riscv/riscv.c (riscv_expand_block_move): Get RTL value
            after type checking.

    gcc/testsuite/ChangeLog:

            PR target/99702
            * gcc.target/riscv/pr99702.c: New.

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since g:d9f0ade001533c9544bf2153b6baa8844ec0bee4

[kito at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

Kito Cheng <kito at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #7 from Kito Cheng <kito at gcc dot gnu.org> ---
Hi Martin, Zdenek:

Thanks you guys!

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since g:d9f0ade001533c9544bf2153b6baa8844ec0bee4

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

--- Comment #8 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-10 branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:e1aa525179b72fb7ea7822c794ec844893ed47e4

commit r10-9506-ge1aa525179b72fb7ea7822c794ec844893ed47e4
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Mon Mar 22 16:32:45 2021 +0800

    PR target/99702: Check RTL type before get value

    gcc/ChangeLog:

            PR target/99702
            * config/riscv/riscv.c (riscv_expand_block_move): Get RTL value
            after type checking.

    gcc/testsuite/ChangeLog:

            PR target/99702
            * gcc.target/riscv/pr99702.c: New.

    (cherry picked from commit 540dace2ed3949571f2ce6cb007354e69bda0cb2)

[Bug target/99702] [11 Regression] ICE: RTL check: expected code 'const_int', have 'subreg' in riscv_expand_block_move, at config/riscv/riscv.c:3262 with memcpy() since g:d9f0ade001533c9544bf2153b6baa8844ec0bee4

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=99702

--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-9 branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:3100cdf24a88aecc428e77fc8a4268947836d66c

commit r9-9301-g3100cdf24a88aecc428e77fc8a4268947836d66c
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Mon Mar 22 16:32:45 2021 +0800

    PR target/99702: Check RTL type before get value

    gcc/ChangeLog:

            PR target/99702
            * config/riscv/riscv.c (riscv_expand_block_move): Get RTL value
            after type checking.

    gcc/testsuite/ChangeLog:

            PR target/99702
            * gcc.target/riscv/pr99702.c: New.

    (cherry picked from commit 540dace2ed3949571f2ce6cb007354e69bda0cb2)