public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work070)] Revert patches.
@ 2021-10-05 21:57 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-10-05 21:57 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1a22213bd37aacf8385bc39cf0043d7964931f4f
commit 1a22213bd37aacf8385bc39cf0043d7964931f4f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 5 17:56:22 2021 -0400
Revert patches.
2021-10-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can use
LXVKQ, it is an easy floating point constant.
(easy_fp_constant_ieee128): New predicate.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate):
New declaration.
* config/rs6000/rs6000.c (xxspltidp_constant_immediate): New
function.
(output_vec_const_move): Add support for LXVKQ.
(rs6000_output_move_128bit): Likewise.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eF): New constraint.
(eV): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can load
the scalar constant with XXSPLTIDP, the constant is easy.
(easy_fp_constant_64bit_scalar): New predicate.
(easy_vector_constant_64bit_element): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate): New
declaration.
(prefixed_xxsplti_p): Likewise.
* config/rs6000/rs6000.c (xxspltidp_constant_immediate): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(prefixed_xxsplti_p): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for the
xxsplti* prefixed instructions.
(movsf_hardfloat): Add XXSPLTIDP support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (vsx_move<mode>_64bit): Add XXSPLTIDP
support.
(vsx_move<mode>_32bit): Likewise.
(XXSPLTIDP_S): New mode iterator.
(XXSPLTIDP_V): Likewise.
(XXSPLTIDP): Likewise.
(xxspltidp_<mode>_inst): Replace xxspltidp_v2df_inst with an
iterated form that also does SFmode, DFmode, DImode, and
V2DImode.
(xxspltidp_<mode>_internal): New insn and splits.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eF and eV constraints.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 15 --
gcc/config/rs6000/predicates.md | 218 ---------------------
gcc/config/rs6000/rs6000-protos.h | 3 -
gcc/config/rs6000/rs6000.c | 198 -------------------
gcc/config/rs6000/rs6000.md | 58 ++----
gcc/config/rs6000/rs6000.opt | 8 -
gcc/config/rs6000/vsx.md | 60 +-----
gcc/doc/md.texi | 9 -
.../gcc.target/powerpc/float128-constant.c | 144 --------------
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ------
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 -------
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ------
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ------
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 -----
14 files changed, 22 insertions(+), 995 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 1700657abe9..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,26 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; DI/SF/DF scalar constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eF"
- "A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_fp_constant_64bit_scalar"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; V2DI/V2DF vector constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eV"
- "A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_vector_constant_64bit_element"))
-
-;; KF/TF scalar than can be loaded with LXVKQ
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_fp_constant_ieee128"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 30e89ec79f0..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,16 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (easy_fp_constant_64bit_scalar (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded
- with that instruction. */
- if (easy_fp_constant_ieee128 (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -619,138 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit scalar constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a V2DF or
-;; V2DI mode result that is interpretted as a 64-bit scalar.
-(define_predicate "easy_fp_constant_64bit_scalar"
- (match_code "const_int,const_double")
-{
- const REAL_VALUE_TYPE *rv;
- REAL_VALUE_TYPE rv_type;
-
- /* Can we do the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- /* Don't return true for 0.0 or 0 since that is easy to create without
- XXSPLTIDP. */
- if (op == CONST0_RTX (mode))
- return false;
-
- /* Handle DImode by creating a DF value from it. */
- if (CONST_INT_P (op) && (mode == DImode || mode == VOIDmode))
- {
- HOST_WIDE_INT df_value = INTVAL (op);
-
- /* Avoid values that look like DFmode NaN's. The IEEE 754 64-bit
- floating format has 1 bit for sign, 11 bits for the exponent,
- and 52 bits for the mantissa. NaN values have the exponent set
- to all 1 bits, and the mantissa non-zero (mantissa == 0 is
- infinity). */
- int df_exponent = (df_value >> 52) & 0x7ff;
- HOST_WIDE_INT df_mantissa = df_value & HOST_WIDE_INT_C (0x1fffffffffffff);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* NaN. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers
- have the exponent all 0 bits, and the mantissa non-zero. If the
- value is subnormal, then the hidden bit in the mantissa is not
- set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
-
- long df_words[2];
- df_words[0] = (df_value >> 32) & 0xffffffff;
- df_words[1] = df_value & 0xffffffff;
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- real_from_target (&rv_type, df_words, DFmode);
- rv = &rv_type;
- }
-
- /* Handle SFmode/DFmode constants. Don't allow decimal or IEEE 128-bit
- binary constants. */
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- rv = CONST_DOUBLE_REAL_VALUE (op);
-
- /* We can't handle anything else with the XXSPLTIDP instruction. */
- else
- return false;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- return true;
-})
-
-;; Return 1 if the operand is a 64-bit vector constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a
-;; V2DFmode or V2DI result.
-;;
-;; We cannot combine the scalar and vector cases because otherwise it is
-;; problematical if we assign an appropriate integer constant to a TImode
-;; value. I.e.
-;;
-;; (set (reg:TI 32)
-;; (const_int 0x8000000000000000))
-;;
-;; Otherwise, the constant would be splatted into the 2 64-bit positions in the
-;; vector register, and not loaded with the upper 64-bits 0, and the constant
-;; in the lower 64-bits.
-
-(define_predicate "easy_vector_constant_64bit_element"
- (match_code "const_vector,vec_duplicate")
-{
- /* Can we do the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (mode != V2DFmode && mode != V2DImode)
- return false;
-
- if (CONST_VECTOR_P (op))
- {
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- op = CONST_VECTOR_ELT (op, 0);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- op = XEXP (op, 0);
-
- else
- return false;
-
- return easy_fp_constant_64bit_scalar (op, GET_MODE_INNER (mode));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -782,79 +640,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is an IEEE 128-bit special constant that can be
-;; loaded with the LXVKQ instruction.
-(define_predicate "easy_fp_constant_ieee128"
- (match_code "const_double")
-{
- if (!TARGET_LXVKQ || !TARGET_POWER10 || !TARGET_VSX || !TARGET_FLOAT128_HW)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IEEE_P (mode))
- return false;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- /* Special values (+/-infinity, -0.0. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- if (real_isinf (rv) || real_isnegzero (rv))
- return true;
-
- /* Only recognize the normal NaN. Do not recognize NaNs with the negative
- sign, signaling NaNs, or NaNs that have non-zero mantissa. */
- if (real_isnan (rv))
- {
- long w[4];
-
- real_to_target (&w[0], rv, mode);
- return (BYTES_BIG_ENDIAN
- ? (w[0] == 0x7fff8000 && w[1] == 0 && w[2] == 0 && w[3] == 0)
- : (w[3] == 0x7fff8000 && w[2] == 0 && w[1] == 0 && w[0] == 0));
- }
-
- if (real_issignaling_nan (rv))
- return false;
-
- /* All of the values generated can be expressed as SFmode values, if it
- doesn't fit in SFmode, exit. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* The other values are all integers 1..7, and -1..-7. */
- if (!real_isinteger (rv, mode))
- return false;
-
- HOST_WIDE_INT value = real_to_integer (rv);
- switch (value)
- {
- default:
- break;
-
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case -1:
- case -2:
- case -3:
- case -4:
- case -5:
- case -6:
- case -7:
- return true;
- }
-
- /* We can't load the value with LXVKQ. */
- return false;
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -868,9 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (easy_vector_constant_64bit_element (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index a21fa08b367..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,8 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern long xxspltidp_constant_immediate (rtx, machine_mode);
-extern int lxvkq_constant_immediate (rtx, machine_mode);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
@@ -200,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 7b0b5357f0b..ad860728169 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6946,150 +6946,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the immediate value used in the XXSPLTIDP instruction. */
-
-long
-xxspltidp_constant_immediate (rtx op, machine_mode mode)
-{
- long ret;
-
- /* Handle vectors. */
- if (CONST_VECTOR_P (op))
- {
- op = CONST_VECTOR_ELT (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- {
- op = XEXP (op, 0);
- mode = GET_MODE (op);
- }
-
- gcc_assert (easy_fp_constant_64bit_scalar (op, mode));
-
- /* Handle DImode/V2DImode by creating a DF value from it and then converting
- the DFmode value to SFmode. */
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT df_value = INTVAL (op);
- long df_words[2];
-
- df_words[0] = (df_value >> 32) & 0xffffffff;
- df_words[1] = df_value & 0xffffffff;
-
- /* real_to_target takes input in target endian order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE r;
- real_from_target (&r, &df_words[0], DFmode);
- real_to_target (&ret, &r, SFmode);
- }
-
- /* For floating point constants, convert to SFmode. */
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- {
- const REAL_VALUE_TYPE *rv = CONST_DOUBLE_REAL_VALUE (op);
- real_to_target (&ret, rv, SFmode);
- }
-
- else
- gcc_unreachable ();
-
- return ret;
-}
-
-/* Return the constant that will go in the LXVKQ instruction. */
-
-/* LXVKQ immediates. */
-enum {
- LXVKQ_ONE = 1,
- LXVKQ_TWO = 2,
- LXVKQ_THREE = 3,
- LXVKQ_FOUR = 4,
- LXVKQ_FIVE = 5,
- LXVKQ_SIX = 6,
- LXVKQ_SEVEN = 7,
- LXVKQ_INF = 8,
- LXVKQ_NAN = 9,
- LXVKQ_NEG_ZERO = 16,
- LXVKQ_NEG_ONE = 17,
- LXVKQ_NEG_TWO = 18,
- LXVKQ_NEG_THREE = 19,
- LXVKQ_NEG_FOUR = 20,
- LXVKQ_NEG_FIVE = 21,
- LXVKQ_NEG_SIX = 22,
- LXVKQ_NEG_SEVEN = 23,
- LXVKQ_NEG_INF = 24
-};
-
-int
-lxvkq_constant_immediate (rtx op, machine_mode mode)
-{
- int ret = -1;
- gcc_assert (easy_fp_constant_ieee128 (op, mode));
-
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
-
- gcc_assert (!real_issignaling_nan (rv));
-
- /* Special values (infinity, nan, -0.0. */
- if (real_isinf (rv))
- ret = real_isneg (rv) ? LXVKQ_NEG_INF : LXVKQ_INF;
-
- /* Only recognize the normal NaN. Do not recognize NaNs with the negative
- sign, signaling NaNs, or NaNs that have non-zero mantissa. */
- else if (real_isnan (rv))
- {
- long w[4];
-
- real_to_target (&w[0], rv, mode);
- gcc_assert (BYTES_BIG_ENDIAN
- ? (w[0] == 0x7fff8000 && w[1] == 0 && w[2] == 0
- && w[3] == 0)
- : (w[3] == 0x7fff8000 && w[2] == 0 && w[1] == 0
- && w[0] == 0));
-
- ret = LXVKQ_NAN;
- }
-
- else if (real_isnegzero (rv))
- ret = LXVKQ_NEG_ZERO;
-
- else
- {
- HOST_WIDE_INT value = real_to_integer (rv);
- switch (value)
- {
- default:
- gcc_unreachable ();
-
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- ret = LXVKQ_ONE + (value - 1);
- break;
-
- case -1:
- case -2:
- case -3:
- case -4:
- case -5:
- case -6:
- case -7:
- ret = LXVKQ_NEG_ONE + (-value - 1);
- break;
- }
- }
-
- return ret;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -7134,19 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (easy_fp_constant_64bit_scalar (vec, mode)
- || easy_vector_constant_64bit_element (vec, mode))
- {
- operands[2] = GEN_INT (xxspltidp_constant_immediate (vec, mode));
- return "xxspltidp %x0,%2";
- }
-
- if (easy_fp_constant_ieee128 (vec, mode))
- {
- operands[2] = GEN_INT (lxvkq_constant_immediate (vec, mode));
- return "lxvkq %x0,%2";
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -13989,12 +13832,6 @@ rs6000_output_move_128bit (rtx operands[])
}
/* Constants. */
- else if (dest_vsx_p && easy_fp_constant_ieee128 (src, mode))
- {
- operands[2] = GEN_INT (lxvkq_constant_immediate (src, mode));
- return "lxvkq %x0,%2";
- }
-
else if (dest_regno >= 0
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
@@ -26887,41 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- switch (mode)
- {
- case E_DImode:
- case E_DFmode:
- case E_SFmode:
- return easy_fp_constant_64bit_scalar (src, mode);
-
- case E_V2DImode:
- case E_V2DFmode:
- return easy_vector_constant_64bit_element (src, mode);
-
- default:
- break;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8afc4b2756d..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eF,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eF,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c9eb78952d6..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,14 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index d7e58654ded..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1191,19 +1191,16 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP LXVKQ
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa, wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eV, eQ,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1215,44 +1212,36 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm, vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *, *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *, *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *, *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP LXVKQ
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eV, eQ,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1264,17 +1253,14 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm, vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *,
*, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10,
p9v, *, <VSisa>, *, *,
*, *")])
@@ -6463,53 +6449,15 @@
DONE;
})
-(define_mode_iterator XXSPLTIDP_S [DI SF DF])
-(define_mode_iterator XXSPLTIDP_V [V2DF V2DI])
-(define_mode_iterator XXSPLTIDP [DI SF DF V2DF V2DI])
-
-(define_insn "xxspltidp_<mode>_inst"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIDP))]
"TARGET_POWER10"
"xxspltidp %x0,%1"
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and V2DF and V2DI vector constants where both elements are
-;; the same. The constant has to be expressible as a SFmode constant that is
-;; not a SFmode denormal value.
-(define_insn_and_split "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP_S 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP_S 1 "easy_fp_constant_64bit_scalar" "eF"))]
- "TARGET_POWER10"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP_S [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- long immediate = xxspltidp_constant_immediate (operands[1], <MODE>mode);
- operands[2] = GEN_INT (immediate);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP_V 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP_V 1 "easy_vector_constant_64bit_element" "eV"))]
- "TARGET_POWER10"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP_V [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- long immediate = xxspltidp_constant_immediate (operands[1], <MODE>mode);
- operands[2] = GEN_INT (immediate);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 813d6316d8c..2b41cb7fb7b 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,18 +3333,9 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eF
-A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction.
-
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eQ
-An IEEE 128-bit constant that can be loaded with the LXVKQ instruction.
-
-@item eV
-A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index 23ee7e85d84..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work070)] Revert patches.
@ 2021-10-05 23:29 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-10-05 23:29 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9c95829611e84fde8b9dda88d76b7e0213221c71
commit 9c95829611e84fde8b9dda88d76b7e0213221c71
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 5 19:28:42 2021 -0400
Revert patches.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(easy_vector_constant_2insns): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_immediate):
New declaration.
* config/rs6000/rs6000.c (xxsplti32dx_constant_immediate): New
helper function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(rs6000_output_move_128bit): Likewise.
(prefixed_xxsplti_p): Constants loaded with XXSPLTI32DX are
prefixed.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(vsx_mov<mode>_64bit): Add support for constants loaded with
XXSPLTI32DX.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTI32DX): New mode iterator.
(splitter for XXSPLTI32DX): Add splitter for constants loaded with
XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insns.
(xxsplti32dx_<mode>_second): New insns.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
Diff:
---
gcc/config/rs6000/constraints.md | 6 --
gcc/config/rs6000/predicates.md | 62 --------------------
gcc/config/rs6000/rs6000-protos.h | 1 -
gcc/config/rs6000/rs6000.c | 65 +--------------------
gcc/config/rs6000/rs6000.md | 119 +++++++++-----------------------------
gcc/config/rs6000/rs6000.opt | 5 --
gcc/config/rs6000/vsx.md | 107 +++++-----------------------------
gcc/doc/md.texi | 3 -
8 files changed, 44 insertions(+), 324 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index f9d1d1ab446..46daeb0861c 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -213,12 +213,6 @@
"A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction."
(match_operand 0 "easy_fp_constant_64bit_scalar"))
-;; DImode, DFmode, V2DImode, V2DFmode constant that can be loaded with 2
-;; XXSPLTI32DX instruction.
-(define_constraint "eD"
- "A constant that can be loaded with a pair of XXSPLTI32DX instructions."
- (match_operand 0 "easy_vector_constant_2insns"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 49b0cb2a060..9b9f5934e58 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -611,11 +611,6 @@
if (easy_fp_constant_ieee128 (op, mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can be
- loaded with a pair of instructions. */
- if (easy_vector_constant_2insns (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -756,60 +751,6 @@
return easy_fp_constant_64bit_scalar (op, GET_MODE_INNER (mode));
})
-;; Return 1 if the operand is either a DImode/DFmode scalar constant or
-;; V2DImode/V2DFmode vector constant that needs 2 XXSPLTI32DX instructions to
-;; load the value
-
-(define_predicate "easy_vector_constant_2insns"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- /* Can we do the XXSPLTI32DX instruction? */
- if (!TARGET_XXSPLTI32DX || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- /* Convert vector constant/duplicate into a scalar. */
- if (CONST_VECTOR_P (op))
- {
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- op = CONST_VECTOR_ELT (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- {
- op = XEXP (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- if (GET_MODE_SIZE (mode) > 8)
- return false;
-
- /* 0.0 or 0 is easy to generate. */
- if (op == CONST0_RTX (mode))
- return false;
-
- /* If we can load up the constant in other ways (either a single load
- constant and a direct move or XXSPLTIDP), don't generate the
- XXSPLTI32DX. */
- if (CONST_INT_P (op))
- return !(satisfies_constraint_I (op)
- || satisfies_constraint_L (op)
- || satisfies_constraint_eI (op)
- || easy_fp_constant_64bit_scalar (op, mode));
-
- /* For floating point, if we can use XXSPLTIDP, we don't want to
- generate XXSPLTI32DX's. */
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- return !easy_fp_constant_64bit_scalar (op, mode);
-
- return false;
-})
-
;; Return 1 if the operand is a constant that can be loaded with the XXSPLTIW
;; instruction that loads up a 32-bit immediate and splats it into the vector.
@@ -1031,9 +972,6 @@
if (easy_vector_constant_splat_word (op, mode))
return true;
- if (easy_vector_constant_2insns (op, mode))
- return 1;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index f517624cc56..540c401e7ad 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,7 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern void xxsplti32dx_constant_immediate (rtx, machine_mode, long *, long *);
extern long xxspltidp_constant_immediate (rtx, machine_mode);
extern long xxspltiw_constant_immediate (rtx, machine_mode);
extern int lxvkq_constant_immediate (rtx, machine_mode);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 6bd34444c07..f93a7c80801 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6951,59 +6951,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-void
-xxsplti32dx_constant_immediate (rtx op,
- machine_mode mode,
- long *high_ptr,
- long *low_ptr)
-{
- gcc_assert (easy_vector_constant_2insns (op, mode));
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (CONST_VECTOR_P (op))
- {
- op = CONST_VECTOR_ELT (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- {
- op = XEXP (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT value = INTVAL (op);
- *high_ptr = (value >> 32) & 0xffffffff;
- *low_ptr = value & 0xffffffff;
- return;
- }
-
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- {
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to
- undo this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0] & 0xffffffff;
- *low_ptr = high_low[1] & 0xffffffff;
- return;
- }
-
- gcc_unreachable ();
-}
-
/* Return the immediate value used in the XXSPLTIDP instruction. */
long
@@ -7287,9 +7234,6 @@ output_vec_const_move (rtx *operands)
return "lxvkq %x0,%2";
}
- if (easy_vector_constant_2insns (vec, mode))
- return "#";
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -14138,9 +14082,6 @@ rs6000_output_move_128bit (rtx operands[])
return "lxvkq %x0,%2";
}
- else if (dest_vsx_p && easy_vector_constant_2insns (src, mode))
- return "#";
-
else if (dest_regno >= 0
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
@@ -27055,13 +26996,11 @@ prefixed_xxsplti_p (rtx_insn *insn)
case E_DImode:
case E_DFmode:
case E_SFmode:
- return (easy_fp_constant_64bit_scalar (src, mode)
- || easy_vector_constant_2insns (src, mode));
+ return easy_fp_constant_64bit_scalar (src, mode);
case E_V2DImode:
case E_V2DFmode:
- return (easy_vector_constant_64bit_element (src, mode)
- || easy_vector_constant_2insns (src, mode));
+ return easy_vector_constant_64bit_element (src, mode);
case E_V16QImode:
case E_V8HImode:
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5c120ef1672..8afc4b2756d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7764,17 +7764,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP XXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0, eF"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7797,24 +7797,15 @@
mt%0 %1
mf%1 %0
nop
- #
#"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *, vecperm")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *, p10")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8074,18 +8065,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR XXSPLTIDP
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r, eF"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8103,29 +8094,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two, vecperm")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
+ 8, 8, 8, *")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")])
+ *, *, *, p10")])
;; STW LWZ MR G-const H-const F-const
@@ -8152,19 +8134,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD XXSPLTIDP
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r, eF"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8187,29 +8169,18 @@
nop
mfvsrd %0,%x1
mtvsrd %x0,%1
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr, vecperm")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, p8v, p8v, p10")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9257,7 +9228,7 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP XXSPLTI32DX
+;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9265,13 +9236,13 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa, ^wa,
+ ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eF, eD,
+ eF,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9287,7 +9258,6 @@
fmr %0,%1
#
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9302,32 +9272,20 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm, vecperm,
+ vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *, *,
+ *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, *,
- *")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, *,
- *")
(set_attr "isa"
"*, *, *, *, *, *,
- p10, p10,
+ p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9363,7 +9321,7 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP XXSPLTI32DX
+;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9374,7 +9332,7 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa, ^wa,
+ ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9384,7 +9342,7 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eF, eD,
+ eF,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9400,7 +9358,6 @@
ld%U1%X1 %0,%1
mr %0,%1
#
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9427,7 +9384,7 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm, vecperm,
+ vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9438,7 +9395,7 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *, *,
+ *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9446,29 +9403,9 @@
8, *,
*, *, *,
*, *")
- (set_attr "num_insns"
- "*, *, *,
- *, 2,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- 8, *,
- *, *, *,
- *, *")
- (set_attr "max_prefixed_insns"
- "*, *, *,
- *, 2,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- 8, *,
- *, *, *,
- *, *")
(set_attr "isa"
"*, *, *,
- p10, p10,
+ p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 898bc4e9e6e..a53aad72547 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,11 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-;; Do not enable at this time.
-mxxsplti32dx
-Target Undocumented Var(TARGET_XXSPLTI32DX) Init(0) Save
-Generate (do not generate) XXSPLTI32DX instructions.
-
mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index cc21c454491..712e5df0c02 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -376,7 +376,6 @@
UNSPEC_XXSPLTIW
UNSPEC_XXSPLTIDP
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -1192,19 +1191,19 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP XXSPLTIW LXVKQ XXSPLTI32DX
+;; XXSPLTIDP XXSPLTIW LXVKQ
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa, wa, wa, wa,
+ wa, wa, wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eV, eW, eQ, eD,
+ eV, eW, eQ,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1216,44 +1215,44 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm, vecperm, vecperm, vecperm,
+ vecperm, vecperm, vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *, *, *, 2,
+ *, *, *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *, *, *, 2,
+ *, *, *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *, *, *, *,
+ *, *, *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10, p10,
+ p10, p10, p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP XXSPLTIW LXVKQ XXSPLTI32DX
+;; XXSPLTIDP XXSPLTIW LXVKQ
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, wa, wa, wa,
+ wa, wa, wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eV, eW, eQ, eD,
+ eV, eW, eQ,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1265,27 +1264,17 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm, vecperm, vecperm, vecperm,
+ vecperm, vecperm, vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *, *,
+ *, *, *,
*, *, *, 20, 16,
*, *")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, 2,
- *, *, *, *, *,
- *, *")
- (set_attr "length"
- "*, *, *, *, *, *,
- *, *, *, 2,
- *, *, *, *, *,
- *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10, p10,
+ p10, p10, p10,
p9v, *, <VSisa>, *, *,
*, *")])
@@ -6581,74 +6570,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [DI SF DF V2DF V2DI])
-
-;; Don't split DImode before register allocation, so that it has a better
-;; chance of winding up in a GPR register.
-(define_split
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand")
- (match_operand:XXSPLTI32DX 1 "easy_vector_constant_2insns"))]
- "TARGET_POWER10 && (reload_completed || <MODE>mode != DImode)"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- long high = 0, low = 0;
-
- xxsplti32dx_constant_immediate (operands[1], <MODE>mode, &high, &low);
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB/XXLXOR/XXLORC instruction instead the first
- XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-})
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxlxor %x0,%x0,%x0
- xxlorc %x0,%x0,%x0
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "veclogical,veclogical,vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-
;; XXBLEND built-in function support
(define_insn "xxblend_<mode>"
[(set (match_operand:VM3 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index feaa205291a..4ad0e745c94 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,9 +3333,6 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eD
-A constant that can be loaded with a pair of XXSPLTI32DX instructions.
-
@item eF
A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction.
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work070)] Revert patches.
@ 2021-10-05 21:49 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-10-05 21:49 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c7126acebb27d7b46d8b2f178cfade0cab259cbd
commit c7126acebb27d7b46d8b2f178cfade0cab259cbd
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 5 17:45:57 2021 -0400
Revert patches.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v2di-2.c: New test.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(easy_vector_constant_2insns): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_immediate):
New declaration.
* config/rs6000/rs6000.c (xxsplti32dx_constant_immediate): New
helper function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(rs6000_output_move_128bit): Likewise.
(prefixed_xxsplti_p): Constants loaded with XXSPLTI32DX are
prefixed.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(vsx_mov<mode>_64bit): Add support for constants loaded with
XXSPLTI32DX.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTI32DX): New mode iterator.
(splitter for XXSPLTI32DX): Add splitter for constants loaded with
XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insns.
(xxsplti32dx_<mode>_second): New insns.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-df-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-di-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di-2.c: New test.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (easy_vector_constant_splat_word):
New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-protos.h (xxspltiw_constant_immediate): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): Don't return true
if we could generate XXSPLTIW instead of XXSPLTIB and sign
extend.
(xxspltiw_constant_immediate): New function.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(prefixed_xxsplti_p): Recognize xxspltiw instructions as
prefixed.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eW constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
2021-10-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can use
LXVKQ, it is an easy floating point constant.
(easy_fp_constant_ieee128): New predicate.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate):
New declaration.
* config/rs6000/rs6000.c (xxspltidp_constant_immediate): New
function.
(output_vec_const_move): Add support for LXVKQ.
(rs6000_output_move_128bit): Likewise.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eF): New constraint.
(eV): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can load
the scalar constant with XXSPLTIDP, the constant is easy.
(easy_fp_constant_64bit_scalar): New predicate.
(easy_vector_constant_64bit_element): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate): New
declaration.
(prefixed_xxsplti_p): Likewise.
* config/rs6000/rs6000.c (xxspltidp_constant_immediate): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(prefixed_xxsplti_p): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for the
xxsplti* prefixed instructions.
(movsf_hardfloat): Add XXSPLTIDP support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (vsx_move<mode>_64bit): Add XXSPLTIDP
support.
(vsx_move<mode>_32bit): Likewise.
(XXSPLTIDP_S): New mode iterator.
(XXSPLTIDP_V): Likewise.
(XXSPLTIDP): Likewise.
(xxspltidp_<mode>_inst): Replace xxspltidp_v2df_inst with an
iterated form that also does SFmode, DFmode, DImode, and
V2DImode.
(xxspltidp_<mode>_internal): New insn and splits.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eF and eV constraints.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 --
gcc/config/rs6000/predicates.md | 140 ---------------------
gcc/config/rs6000/rs6000-protos.h | 2 -
gcc/config/rs6000/rs6000.c | 96 --------------
gcc/config/rs6000/rs6000.md | 58 +++------
gcc/config/rs6000/rs6000.opt | 4 -
gcc/config/rs6000/vsx.md | 60 +--------
gcc/doc/md.texi | 6 -
.../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +-
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 ---------
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 -----------
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ---------
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ----------
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 --------
14 files changed, 26 insertions(+), 663 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 1ff46c9f4fc..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,21 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; DI/SF/DF scalar constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eF"
- "A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_fp_constant_64bit_scalar"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; V2DI/V2DF vector constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eV"
- "A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_vector_constant_64bit_element"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 7544ac87700..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,11 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (easy_fp_constant_64bit_scalar (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -614,138 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit scalar constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a V2DF or
-;; V2DI mode result that is interpretted as a 64-bit scalar.
-(define_predicate "easy_fp_constant_64bit_scalar"
- (match_code "const_int,const_double")
-{
- const REAL_VALUE_TYPE *rv;
- REAL_VALUE_TYPE rv_type;
-
- /* Can we do the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- /* Don't return true for 0.0 or 0 since that is easy to create without
- XXSPLTIDP. */
- if (op == CONST0_RTX (mode))
- return false;
-
- /* Handle DImode by creating a DF value from it. */
- if (CONST_INT_P (op) && (mode == DImode || mode == VOIDmode))
- {
- HOST_WIDE_INT df_value = INTVAL (op);
-
- /* Avoid values that look like DFmode NaN's. The IEEE 754 64-bit
- floating format has 1 bit for sign, 11 bits for the exponent,
- and 52 bits for the mantissa. NaN values have the exponent set
- to all 1 bits, and the mantissa non-zero (mantissa == 0 is
- infinity). */
- int df_exponent = (df_value >> 52) & 0x7ff;
- HOST_WIDE_INT df_mantissa = df_value & HOST_WIDE_INT_C (0x1fffffffffffff);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* NaN. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers
- have the exponent all 0 bits, and the mantissa non-zero. If the
- value is subnormal, then the hidden bit in the mantissa is not
- set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
-
- long df_words[2];
- df_words[0] = (df_value >> 32) & 0xffffffff;
- df_words[1] = df_value & 0xffffffff;
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- real_from_target (&rv_type, df_words, DFmode);
- rv = &rv_type;
- }
-
- /* Handle SFmode/DFmode constants. Don't allow decimal or IEEE 128-bit
- binary constants. */
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- rv = CONST_DOUBLE_REAL_VALUE (op);
-
- /* We can't handle anything else with the XXSPLTIDP instruction. */
- else
- return false;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- return true;
-})
-
-;; Return 1 if the operand is a 64-bit vector constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a
-;; V2DFmode or V2DI result.
-;;
-;; We cannot combine the scalar and vector cases because otherwise it is
-;; problematical if we assign an appropriate integer constant to a TImode
-;; value. I.e.
-;;
-;; (set (reg:TI 32)
-;; (const_int 0x8000000000000000))
-;;
-;; Otherwise, the constant would be splatted into the 2 64-bit positions in the
-;; vector register, and not loaded with the upper 64-bits 0, and the constant
-;; in the lower 64-bits.
-
-(define_predicate "easy_vector_constant_64bit_element"
- (match_code "const_vector,vec_duplicate")
-{
- /* Can we do the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (mode != V2DFmode && mode != V2DImode)
- return false;
-
- if (CONST_VECTOR_P (op))
- {
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- op = CONST_VECTOR_ELT (op, 0);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- op = XEXP (op, 0);
-
- else
- return false;
-
- return easy_fp_constant_64bit_scalar (op, GET_MODE_INNER (mode));
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -790,9 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (easy_vector_constant_64bit_element (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index e9be9c4d99f..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,7 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern long xxspltidp_constant_immediate (rtx, machine_mode);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
@@ -199,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 83d243269e3..ad860728169 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6946,60 +6946,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the immediate value used in the XXSPLTIDP instruction. */
-
-long
-xxspltidp_constant_immediate (rtx op, machine_mode mode)
-{
- long ret;
-
- /* Handle vectors. */
- if (CONST_VECTOR_P (op))
- {
- op = CONST_VECTOR_ELT (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- {
- op = XEXP (op, 0);
- mode = GET_MODE (op);
- }
-
- gcc_assert (easy_fp_constant_64bit_scalar (op, mode));
-
- /* Handle DImode/V2DImode by creating a DF value from it and then converting
- the DFmode value to SFmode. */
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT df_value = INTVAL (op);
- long df_words[2];
-
- df_words[0] = (df_value >> 32) & 0xffffffff;
- df_words[1] = df_value & 0xffffffff;
-
- /* real_to_target takes input in target endian order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE r;
- real_from_target (&r, &df_words[0], DFmode);
- real_to_target (&ret, &r, SFmode);
- }
-
- /* For floating point constants, convert to SFmode. */
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- {
- const REAL_VALUE_TYPE *rv = CONST_DOUBLE_REAL_VALUE (op);
- real_to_target (&ret, rv, SFmode);
- }
-
- else
- gcc_unreachable ();
-
- return ret;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -7044,13 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (easy_fp_constant_64bit_scalar (vec, mode)
- || easy_vector_constant_64bit_element (vec, mode))
- {
- operands[2] = GEN_INT (xxspltidp_constant_immediate (vec, mode));
- return "xxspltidp %x0,%2";
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -26785,41 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- switch (mode)
- {
- case E_DImode:
- case E_DFmode:
- case E_SFmode:
- return easy_fp_constant_64bit_scalar (src, mode);
-
- case E_V2DImode:
- case E_V2DFmode:
- return easy_vector_constant_64bit_element (src, mode);
-
- default:
- break;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8afc4b2756d..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eF,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eF,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 1d7ce4cc94a..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,10 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index fa33c9d9fbf..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1191,19 +1191,16 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eV,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1215,44 +1212,36 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eV,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1264,17 +1253,14 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *,
*, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10,
p9v, *, <VSisa>, *, *,
*, *")])
@@ -6463,53 +6449,15 @@
DONE;
})
-(define_mode_iterator XXSPLTIDP_S [DI SF DF])
-(define_mode_iterator XXSPLTIDP_V [V2DF V2DI])
-(define_mode_iterator XXSPLTIDP [DI SF DF V2DF V2DI])
-
-(define_insn "xxspltidp_<mode>_inst"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIDP))]
"TARGET_POWER10"
"xxspltidp %x0,%1"
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and V2DF and V2DI vector constants where both elements are
-;; the same. The constant has to be expressible as a SFmode constant that is
-;; not a SFmode denormal value.
-(define_insn_and_split "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP_S 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP_S 1 "easy_fp_constant_64bit_scalar" "eF"))]
- "TARGET_POWER10"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP_S [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- long immediate = xxspltidp_constant_immediate (operands[1], <MODE>mode);
- operands[2] = GEN_INT (immediate);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP_V 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP_V 1 "easy_vector_constant_64bit_element" "eV"))]
- "TARGET_POWER10"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP_V [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- long immediate = xxspltidp_constant_immediate (operands[1], <MODE>mode);
- operands[2] = GEN_INT (immediate);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 5035a3fd604..2b41cb7fb7b 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,15 +3333,9 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eF
-A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction.
-
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eV
-A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
index dcb30e1d886..bd1502bb30a 100644
--- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
+++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c
@@ -24,12 +24,11 @@ vector signed long long splats4(void)
return (vector signed long long) vec_sl(mzero, mzero);
}
-/* Codegen will consist of splat and shift instructions for most types. If
- folding is enabled, the vec_sl tests using vector long long type will
- generate a lvx instead of a vspltisw+vsld pair. On power10, it will
- generate a xxspltidp instruction instead of the lvx. */
+/* Codegen will consist of splat and shift instructions for most types.
+ If folding is enabled, the vec_sl tests using vector long long type will
+ generate a lvx instead of a vspltisw+vsld pair. */
/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */
/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */
-/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work070)] Revert patches.
@ 2021-10-05 21:33 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-10-05 21:33 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d7d72285470faa875a443b9a701891608a81d4dc
commit d7d72285470faa875a443b9a701891608a81d4dc
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 5 17:32:07 2021 -0400
Revert patches.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (easy_vector_constant_splat_word):
New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-protos.h (xxspltiw_constant_immediate): New
declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): Don't return true
if we could generate XXSPLTIW instead of XXSPLTIB and sign
extend.
(xxspltiw_constant_immediate): New function.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(prefixed_xxsplti_p): Recognize xxspltiw instructions as
prefixed.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eW constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eQ): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can use
LXVKQ, it is an easy floating point constant.
(easy_fp_constant_ieee128): New predicate.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate):
New declaration.
* config/rs6000/rs6000.c (xxspltidp_constant_immediate): New
function.
(output_vec_const_move): Add support for LXVKQ.
(rs6000_output_move_128bit): Likewise.
* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
LXVKQ.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eQ constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/float128-constant.c: New test.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eF): New constraint.
(eV): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If we can load
the scalar constant with XXSPLTIDP, the constant is easy.
(easy_fp_constant_64bit_scalar): New predicate.
(easy_vector_constant_64bit_element): New predicate.
(easy_vector_constant): If we can generate XXSPLTIDP, mark the
vector constant as easy.
* config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate): New
declaration.
(prefixed_xxsplti_p): Likewise.
* config/rs6000/rs6000.c (xxspltidp_constant_immediate): New function.
(output_vec_const_move): Add support for XXSPLTIDP.
(prefixed_xxsplti_p): New function.
* config/rs6000/rs6000.md (prefixed attribute): Add support for the
xxsplti* prefixed instructions.
(movsf_hardfloat): Add XXSPLTIDP support.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
* config/rs6000/vsx.md (vsx_move<mode>_64bit): Add XXSPLTIDP
support.
(vsx_move<mode>_32bit): Likewise.
(XXSPLTIDP_S): New mode iterator.
(XXSPLTIDP_V): Likewise.
(XXSPLTIDP): Likewise.
(xxspltidp_<mode>_inst): Replace xxspltidp_v2df_inst with an
iterated form that also does SFmode, DFmode, DImode, and
V2DImode.
(xxspltidp_<mode>_internal): New insn and splits.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eF and eV constraints.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-df.c: New test.
* gcc.target/powerpc/vec-splat-constant-di.c: New test.
* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di.c: New test.
* gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn
regex for power10.
Diff:
---
gcc/config/rs6000/constraints.md | 20 --
gcc/config/rs6000/predicates.md | 319 ---------------------
gcc/config/rs6000/rs6000-protos.h | 4 -
gcc/config/rs6000/rs6000.c | 291 -------------------
gcc/config/rs6000/rs6000.md | 58 ++--
gcc/config/rs6000/rs6000.opt | 13 -
gcc/config/rs6000/vsx.md | 60 +---
gcc/doc/md.texi | 12 -
.../gcc.target/powerpc/float128-constant.c | 144 ----------
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 --
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 -----
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ----
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ----
13 files changed, 22 insertions(+), 1106 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 46daeb0861c..c8cff1a3038 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -208,31 +208,11 @@
(and (match_code "const_int")
(match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000")))
-;; DI/SF/DF scalar constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eF"
- "A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_fp_constant_64bit_scalar"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
(match_operand 0 "cint34_operand"))
-;; V2DI/V2DF vector constant that can be loaded with the XXSPLTIDP instruction.
-(define_constraint "eV"
- "A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction."
- (match_operand 0 "easy_vector_constant_64bit_element"))
-
-;; KF/TF scalar than can be loaded with LXVKQ
-(define_constraint "eQ"
- "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
- (match_operand 0 "easy_fp_constant_ieee128"))
-
-;; Vector constant that can be loaded with XXSPLTIW
-(define_constraint "eW"
- "A vector constant that can be loaded with the XXSPLTIW instruction."
- (match_operand 0 "easy_vector_constant_splat_word"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index 9b9f5934e58..956e42bc514 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -601,16 +601,6 @@
if (TARGET_VSX && op == CONST0_RTX (mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can
- be loaded with that instruction. */
- if (easy_fp_constant_64bit_scalar (op, mode))
- return 1;
-
- /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded
- with that instruction. */
- if (easy_fp_constant_ieee128 (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -619,236 +609,6 @@
return 0;
})
-;; Return 1 if the operand is a 64-bit scalar constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a V2DF or
-;; V2DI mode result that is interpretted as a 64-bit scalar.
-(define_predicate "easy_fp_constant_64bit_scalar"
- (match_code "const_int,const_double")
-{
- const REAL_VALUE_TYPE *rv;
- REAL_VALUE_TYPE rv_type;
-
- /* Can we do the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- /* Don't return true for 0.0 or 0 since that is easy to create without
- XXSPLTIDP. */
- if (op == CONST0_RTX (mode))
- return false;
-
- /* Handle DImode by creating a DF value from it. */
- if (CONST_INT_P (op) && (mode == DImode || mode == VOIDmode))
- {
- HOST_WIDE_INT df_value = INTVAL (op);
-
- /* Avoid values that look like DFmode NaN's. The IEEE 754 64-bit
- floating format has 1 bit for sign, 11 bits for the exponent,
- and 52 bits for the mantissa. NaN values have the exponent set
- to all 1 bits, and the mantissa non-zero (mantissa == 0 is
- infinity). */
- int df_exponent = (df_value >> 52) & 0x7ff;
- HOST_WIDE_INT df_mantissa = df_value & HOST_WIDE_INT_C (0x1fffffffffffff);
-
- if (df_exponent == 0x7ff && df_mantissa != 0) /* NaN. */
- return false;
-
- /* Avoid values that are DFmode subnormal values. Subnormal numbers
- have the exponent all 0 bits, and the mantissa non-zero. If the
- value is subnormal, then the hidden bit in the mantissa is not
- set. */
- if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */
- return false;
-
- long df_words[2];
- df_words[0] = (df_value >> 32) & 0xffffffff;
- df_words[1] = df_value & 0xffffffff;
-
- /* real_from_target takes the target words in target order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- real_from_target (&rv_type, df_words, DFmode);
- rv = &rv_type;
- }
-
- /* Handle SFmode/DFmode constants. Don't allow decimal or IEEE 128-bit
- binary constants. */
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- rv = CONST_DOUBLE_REAL_VALUE (op);
-
- /* We can't handle anything else with the XXSPLTIDP instruction. */
- else
- return false;
-
- /* Validate that the number can be stored as a SFmode value. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* Validate that the number is not a SFmode subnormal value (exponent is 0,
- mantissa field is non-zero) which is undefined for the XXSPLTIDP
- instruction. */
- long sf_value;
- real_to_target (&sf_value, rv, SFmode);
-
- /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent,
- and 23 bits for the mantissa. Subnormal numbers have the exponent all
- 0 bits, and the mantissa non-zero. */
- long sf_exponent = (sf_value >> 23) & 0xFF;
- long sf_mantissa = sf_value & 0x7FFFFF;
-
- if (sf_exponent == 0 && sf_mantissa != 0)
- return false;
-
- return true;
-})
-
-;; Return 1 if the operand is a 64-bit vector constant that can be loaded via
-;; the XXSPLTIDP instruction, which takes a SFmode value and produces a
-;; V2DFmode or V2DI result.
-;;
-;; We cannot combine the scalar and vector cases because otherwise it is
-;; problematical if we assign an appropriate integer constant to a TImode
-;; value. I.e.
-;;
-;; (set (reg:TI 32)
-;; (const_int 0x8000000000000000))
-;;
-;; Otherwise, the constant would be splatted into the 2 64-bit positions in the
-;; vector register, and not loaded with the upper 64-bits 0, and the constant
-;; in the lower 64-bits.
-
-(define_predicate "easy_vector_constant_64bit_element"
- (match_code "const_vector,vec_duplicate")
-{
- /* Can we do the XXSPLTIDP instruction? */
- if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (mode != V2DFmode && mode != V2DImode)
- return false;
-
- if (CONST_VECTOR_P (op))
- {
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- op = CONST_VECTOR_ELT (op, 0);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- op = XEXP (op, 0);
-
- else
- return false;
-
- return easy_fp_constant_64bit_scalar (op, GET_MODE_INNER (mode));
-})
-
-;; Return 1 if the operand is a constant that can be loaded with the XXSPLTIW
-;; instruction that loads up a 32-bit immediate and splats it into the vector.
-
-(define_predicate "easy_vector_constant_splat_word"
- (match_code "const_vector")
-{
- HOST_WIDE_INT value;
-
- if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTIW)
- return false;
-
- rtx element0 = CONST_VECTOR_ELT (op, 0);
-
- switch (mode)
- {
- /* V4SImode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V4SImode:
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- /* Don't return true if we can use the shorter vspltisw instruction. */
- value = INTVAL (element0);
- return (!EASY_VECTOR_15 (value));
-
- /* V4SFmode constant vectors that have the same element are
- can be used with XXSPLTIW. */
- case V4SFmode:
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- /* Don't return true for 0.0f, since that can be created with
- xxspltib or xxlxor. */
- return (element0 != CONST0_RTX (SFmode));
-
- /* V8Hmode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V8HImode:
- if (CONST_VECTOR_DUPLICATE_P (op))
- {
- /* Don't return true if we can use the shorter vspltish instruction. */
- value = INTVAL (element0);
- if (EASY_VECTOR_15 (value))
- return false;
-
- return true;
- }
-
- else
- {
- /* Check if all even elements are the same and all odd elements are
- the same. */
- rtx element1 = CONST_VECTOR_ELT (op, 1);
-
- if (!CONST_INT_P (element1))
- return false;
-
- for (size_t i = 2; i < GET_MODE_NUNITS (V8HImode); i += 2)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1)))
- return false;
-
- return true;
- }
-
- /* V16QI constant vectors that have the first four elements identical to
- the next set of 4 elements, and so forth can generate XXSPLTIW. */
- case V16QImode:
- {
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (xxspltib_constant_nosplit (op, mode))
- return false;
-
- rtx element1 = CONST_VECTOR_ELT (op, 1);
- rtx element2 = CONST_VECTOR_ELT (op, 2);
- rtx element3 = CONST_VECTOR_ELT (op, 3);
-
- if (!CONST_INT_P (element0) || !CONST_INT_P (element1)
- || !CONST_INT_P (element2) || !CONST_INT_P (element3))
- return false;
-
- for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1))
- || !rtx_equal_p (element2, CONST_VECTOR_ELT (op, i + 2))
- || !rtx_equal_p (element3, CONST_VECTOR_ELT (op, i + 3)))
- return false;
-
- return true;
- }
-
- default:
- break;
- }
-
- return false;
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -880,79 +640,6 @@
return num_insns == 1;
})
-;; Return 1 if the operand is an IEEE 128-bit special constant that can be
-;; loaded with the LXVKQ instruction.
-(define_predicate "easy_fp_constant_ieee128"
- (match_code "const_double")
-{
- if (!TARGET_LXVKQ || !TARGET_POWER10 || !TARGET_VSX || !TARGET_FLOAT128_HW)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (!FLOAT128_IEEE_P (mode))
- return false;
-
- if (!CONST_DOUBLE_P (op))
- return false;
-
- /* Special values (+/-infinity, -0.0. */
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- if (real_isinf (rv) || real_isnegzero (rv))
- return true;
-
- /* Only recognize the normal NaN. Do not recognize NaNs with the negative
- sign, signaling NaNs, or NaNs that have non-zero mantissa. */
- if (real_isnan (rv))
- {
- long w[4];
-
- real_to_target (&w[0], rv, mode);
- return (BYTES_BIG_ENDIAN
- ? (w[0] == 0x7fff8000 && w[1] == 0 && w[2] == 0 && w[3] == 0)
- : (w[3] == 0x7fff8000 && w[2] == 0 && w[1] == 0 && w[0] == 0));
- }
-
- if (real_issignaling_nan (rv))
- return false;
-
- /* All of the values generated can be expressed as SFmode values, if it
- doesn't fit in SFmode, exit. */
- if (!exact_real_truncate (SFmode, rv))
- return false;
-
- /* The other values are all integers 1..7, and -1..-7. */
- if (!real_isinteger (rv, mode))
- return false;
-
- HOST_WIDE_INT value = real_to_integer (rv);
- switch (value)
- {
- default:
- break;
-
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- case -1:
- case -2:
- case -3:
- case -4:
- case -5:
- case -6:
- case -7:
- return true;
- }
-
- /* We can't load the value with LXVKQ. */
- return false;
-})
-
;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a
;; vector register without using memory.
(define_predicate "easy_vector_constant"
@@ -966,12 +653,6 @@
if (zero_constant (op, mode) || all_ones_constant (op, mode))
return true;
- if (easy_vector_constant_64bit_element (op, mode))
- return true;
-
- if (easy_vector_constant_splat_word (op, mode))
- return true;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 540c401e7ad..14f6b313105 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,9 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern long xxspltidp_constant_immediate (rtx, machine_mode);
-extern long xxspltiw_constant_immediate (rtx, machine_mode);
-extern int lxvkq_constant_immediate (rtx, machine_mode);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
extern bool macho_lo_sum_memory_operand (rtx, machine_mode);
@@ -201,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode);
extern bool prefixed_load_p (rtx_insn *);
extern bool prefixed_store_p (rtx_insn *);
extern bool prefixed_paddi_p (rtx_insn *);
-extern bool prefixed_xxsplti_p (rtx_insn *);
extern void rs6000_asm_output_opcode (FILE *);
extern void output_pcrel_opt_reloc (rtx);
extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 1172fb999fc..ad860728169 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
- /* If we can generate the constant with a single XXSPLTIW don't generate a
- XXSPLTIB and a sign extend operation. */
- else if (easy_vector_constant_splat_word (op, mode))
- return false;
-
else
*num_insns_ptr = 2;
@@ -6951,226 +6946,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the immediate value used in the XXSPLTIDP instruction. */
-
-long
-xxspltidp_constant_immediate (rtx op, machine_mode mode)
-{
- long ret;
-
- /* Handle vectors. */
- if (CONST_VECTOR_P (op))
- {
- op = CONST_VECTOR_ELT (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- {
- op = XEXP (op, 0);
- mode = GET_MODE (op);
- }
-
- gcc_assert (easy_fp_constant_64bit_scalar (op, mode));
-
- /* Handle DImode/V2DImode by creating a DF value from it and then converting
- the DFmode value to SFmode. */
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT df_value = INTVAL (op);
- long df_words[2];
-
- df_words[0] = (df_value >> 32) & 0xffffffff;
- df_words[1] = df_value & 0xffffffff;
-
- /* real_to_target takes input in target endian order. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (df_words[0], df_words[1]);
-
- REAL_VALUE_TYPE r;
- real_from_target (&r, &df_words[0], DFmode);
- real_to_target (&ret, &r, SFmode);
- }
-
- /* For floating point constants, convert to SFmode. */
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- {
- const REAL_VALUE_TYPE *rv = CONST_DOUBLE_REAL_VALUE (op);
- real_to_target (&ret, rv, SFmode);
- }
-
- else
- gcc_unreachable ();
-
- return ret;
-}
-
-/* Return the immediate value used in the XXSPLTIW instruction. */
-long
-xxspltiw_constant_immediate (rtx op, machine_mode mode)
-{
- long ret;
-
- gcc_assert (easy_vector_constant_splat_word (op, mode));
-
- switch (mode)
- {
- default:
- gcc_unreachable ();
-
- /* V4SImode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case E_V4SImode:
- gcc_assert (CONST_VECTOR_DUPLICATE_P (op));
- ret = INTVAL (CONST_VECTOR_ELT (op, 0));
- break;
-
- /* V4SFmode constant vectors that have the same element are
- can be used with XXSPLTIW. */
- case E_V4SFmode:
- gcc_assert (CONST_VECTOR_DUPLICATE_P (op));
- ret = rs6000_const_f32_to_i32 (CONST_VECTOR_ELT (op, 0));
- break;
-
- /* V8HImode constant vectors with all of the even elements the same and
- all of the odd elements the same can used XXSPLTIW. */
- case E_V8HImode:
- {
- if (!rtx_equal_p (CONST_VECTOR_ELT (op, 0), CONST_VECTOR_ELT (op, 2))
- || !rtx_equal_p (CONST_VECTOR_ELT (op, 1), CONST_VECTOR_ELT (op, 3)))
- gcc_unreachable ();
-
- long value0 = INTVAL (CONST_VECTOR_ELT (op, 0)) & 0xffff;
- long value1 = INTVAL (CONST_VECTOR_ELT (op, 1)) & 0xffff;
-
- if (!BYTES_BIG_ENDIAN)
- std::swap (value0, value1);
-
- ret = (value0 << 16) | value1;
- }
- break;
-
- /* V16QI constant vectors that have the first four elements identical to
- the next set of 4 elements, and so forth can generate XXSPLTIW. */
- case E_V16QImode:
- {
- rtx op0 = CONST_VECTOR_ELT (op, 0);
- rtx op1 = CONST_VECTOR_ELT (op, 1);
- rtx op2 = CONST_VECTOR_ELT (op, 2);
- rtx op3 = CONST_VECTOR_ELT (op, 3);
-
- for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4)
- if (!rtx_equal_p (op0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (op1, CONST_VECTOR_ELT (op, i + 1))
- || !rtx_equal_p (op2, CONST_VECTOR_ELT (op, i + 2))
- || !rtx_equal_p (op3, CONST_VECTOR_ELT (op, i + 3)))
- gcc_unreachable ();
-
- long value0 = INTVAL (op0) & 0xff;
- long value1 = INTVAL (op1) & 0xff;
- long value2 = INTVAL (op2) & 0xff;
- long value3 = INTVAL (op3) & 0xff;
-
- ret = ((BYTES_BIG_ENDIAN)
- ? ((value0 << 24) | (value1 << 16) | (value2 << 8) | value3)
- : ((value3 << 24) | (value2 << 16) | (value1 << 8) | value0));
- }
- break;
- }
-
- return ret;
-}
-
-/* Return the constant that will go in the LXVKQ instruction. */
-
-/* LXVKQ immediates. */
-enum {
- LXVKQ_ONE = 1,
- LXVKQ_TWO = 2,
- LXVKQ_THREE = 3,
- LXVKQ_FOUR = 4,
- LXVKQ_FIVE = 5,
- LXVKQ_SIX = 6,
- LXVKQ_SEVEN = 7,
- LXVKQ_INF = 8,
- LXVKQ_NAN = 9,
- LXVKQ_NEG_ZERO = 16,
- LXVKQ_NEG_ONE = 17,
- LXVKQ_NEG_TWO = 18,
- LXVKQ_NEG_THREE = 19,
- LXVKQ_NEG_FOUR = 20,
- LXVKQ_NEG_FIVE = 21,
- LXVKQ_NEG_SIX = 22,
- LXVKQ_NEG_SEVEN = 23,
- LXVKQ_NEG_INF = 24
-};
-
-int
-lxvkq_constant_immediate (rtx op, machine_mode mode)
-{
- int ret = -1;
- gcc_assert (easy_fp_constant_ieee128 (op, mode));
-
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
-
- gcc_assert (!real_issignaling_nan (rv));
-
- /* Special values (infinity, nan, -0.0. */
- if (real_isinf (rv))
- ret = real_isneg (rv) ? LXVKQ_NEG_INF : LXVKQ_INF;
-
- /* Only recognize the normal NaN. Do not recognize NaNs with the negative
- sign, signaling NaNs, or NaNs that have non-zero mantissa. */
- else if (real_isnan (rv))
- {
- long w[4];
-
- real_to_target (&w[0], rv, mode);
- gcc_assert (BYTES_BIG_ENDIAN
- ? (w[0] == 0x7fff8000 && w[1] == 0 && w[2] == 0
- && w[3] == 0)
- : (w[3] == 0x7fff8000 && w[2] == 0 && w[1] == 0
- && w[0] == 0));
-
- ret = LXVKQ_NAN;
- }
-
- else if (real_isnegzero (rv))
- ret = LXVKQ_NEG_ZERO;
-
- else
- {
- HOST_WIDE_INT value = real_to_integer (rv);
- switch (value)
- {
- default:
- gcc_unreachable ();
-
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
- ret = LXVKQ_ONE + (value - 1);
- break;
-
- case -1:
- case -2:
- case -3:
- case -4:
- case -5:
- case -6:
- case -7:
- ret = LXVKQ_NEG_ONE + (-value - 1);
- break;
- }
- }
-
- return ret;
-}
-
const char *
output_vec_const_move (rtx *operands)
{
@@ -7215,25 +6990,6 @@ output_vec_const_move (rtx *operands)
gcc_unreachable ();
}
- if (easy_fp_constant_64bit_scalar (vec, mode)
- || easy_vector_constant_64bit_element (vec, mode))
- {
- operands[2] = GEN_INT (xxspltidp_constant_immediate (vec, mode));
- return "xxspltidp %x0,%2";
- }
-
- if (easy_vector_constant_splat_word (vec, mode))
- {
- operands[2] = GEN_INT (xxspltiw_constant_immediate (vec, mode));
- return "xxspltiw %x0,%2";
- }
-
- if (easy_fp_constant_ieee128 (vec, mode))
- {
- operands[2] = GEN_INT (lxvkq_constant_immediate (vec, mode));
- return "lxvkq %x0,%2";
- }
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -14076,12 +13832,6 @@ rs6000_output_move_128bit (rtx operands[])
}
/* Constants. */
- else if (dest_vsx_p && easy_fp_constant_ieee128 (src, mode))
- {
- operands[2] = GEN_INT (lxvkq_constant_immediate (src, mode));
- return "lxvkq %x0,%2";
- }
-
else if (dest_regno >= 0
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
@@ -26974,47 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn)
return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL);
}
-/* Whether a permute type instruction is a prefixed XXSPLTI* instruction.
- This is called from the prefixed attribute processing. */
-
-bool
-prefixed_xxsplti_p (rtx_insn *insn)
-{
- rtx set = single_set (insn);
- if (!set)
- return false;
-
- rtx dest = SET_DEST (set);
- rtx src = SET_SRC (set);
- machine_mode mode = GET_MODE (dest);
-
- if (!REG_P (dest) && !SUBREG_P (dest))
- return false;
-
- switch (mode)
- {
- case E_DImode:
- case E_DFmode:
- case E_SFmode:
- return easy_fp_constant_64bit_scalar (src, mode);
-
- case E_V2DImode:
- case E_V2DFmode:
- return easy_vector_constant_64bit_element (src, mode);
-
- case E_V16QImode:
- case E_V8HImode:
- case E_V4SImode:
- case E_V4SFmode:
- return easy_vector_constant_splat_word (src, mode);
-
- default:
- break;
- }
-
- return false;
-}
-
/* Whether the next instruction needs a 'p' prefix issued before the
instruction is printed out. */
static bool prepend_p_to_next_insn;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8afc4b2756d..6bec2bddbde 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -314,11 +314,6 @@
(eq_attr "type" "integer,add")
(if_then_else (match_test "prefixed_paddi_p (insn)")
- (const_string "yes")
- (const_string "no"))
-
- (eq_attr "type" "vecperm")
- (if_then_else (match_test "prefixed_xxsplti_p (insn)")
(const_string "yes")
(const_string "no"))]
@@ -7764,17 +7759,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP
+;; MR MT<x> MF<x> NOP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF"))]
+ r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7796,16 +7791,15 @@
mr %0,%1
mt%0 %1
mf%1 %0
- nop
- #"
+ nop"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm")
+ *, mtjmpr, mfjmpr, *")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10")])
+ *, *, *, *")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8065,18 +8059,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP
+;; LWZ STW MR
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa")
+ Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF"))]
+ r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8093,21 +8087,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm")
+ store, load, two")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *")
+ 8, 8, 8")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10")])
+ *, *, *")])
;; STW LWZ MR G-const H-const F-const
@@ -8134,19 +8127,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP
+;; NOP MFVSRD MTVSRD
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa")
+ *h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF"))]
+ 0, <f64_dm>, r"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8168,19 +8161,18 @@
mf%1 %0
nop
mfvsrd %0,%x1
- mtvsrd %x0,%1
- #"
+ mtvsrd %x0,%1"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm")
+ *, mfvsr, mtvsr")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10")])
+ *, p8v, p8v")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9228,7 +9220,6 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9236,13 +9227,11 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eF,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9257,7 +9246,6 @@
lfd%U1%X1 %0,%1
fmr %0,%1
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9272,20 +9260,17 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
(set_attr "isa"
"*, *, *, *, *, *,
- p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9321,7 +9306,6 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9332,7 +9316,6 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9342,7 +9325,6 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eF,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9357,7 +9339,6 @@
std%U0%X0 %1,%0
ld%U1%X1 %0,%1
mr %0,%1
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9384,7 +9365,6 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9395,7 +9375,6 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9405,7 +9384,6 @@
*, *")
(set_attr "isa"
"*, *, *,
- p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index a53aad72547..9d7878f144a 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,19 +640,6 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-mxxspltidp
-Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
-Generate (do not generate) XXSPLTIDP instructions.
-
-;; Do not enable at this time.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(0) Save
-Generate (do not generate) XXSPLTIW instructions.
-
-mlxvkq
-Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
-Generate (do not generate) LXVKQ instructions.
-
-param=rs6000-density-pct-threshold=
Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param
When costing for loop vectorization, we probably need to penalize the loop body
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 712e5df0c02..bf033e31c1c 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1191,19 +1191,16 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP XXSPLTIW LXVKQ
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa, wa, wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eV, eW, eQ,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1215,44 +1212,36 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm, vecperm, vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *, *, *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *, *, *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *, *, *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP XXSPLTIW LXVKQ
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, wa, wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eV, eW, eQ,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1264,17 +1253,14 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm, vecperm, vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *,
*, *, *, 20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10,
p9v, *, <VSisa>, *, *,
*, *")])
@@ -6463,53 +6449,15 @@
DONE;
})
-(define_mode_iterator XXSPLTIDP_S [DI SF DF])
-(define_mode_iterator XXSPLTIDP_V [V2DF V2DI])
-(define_mode_iterator XXSPLTIDP [DI SF DF V2DF V2DI])
-
-(define_insn "xxspltidp_<mode>_inst"
- [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa")
- (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")]
- UNSPEC_XXSPLTIDP))]
+(define_insn "xxspltidp_v2df_inst"
+ [(set (match_operand:V2DF 0 "register_operand" "=wa")
+ (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")]
+ UNSPEC_XXSPLTIDP))]
"TARGET_POWER10"
"xxspltidp %x0,%1"
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode
-;; scalar constants and V2DF and V2DI vector constants where both elements are
-;; the same. The constant has to be expressible as a SFmode constant that is
-;; not a SFmode denormal value.
-(define_insn_and_split "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP_S 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP_S 1 "easy_fp_constant_64bit_scalar" "eF"))]
- "TARGET_POWER10"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP_S [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- long immediate = xxspltidp_constant_immediate (operands[1], <MODE>mode);
- operands[2] = GEN_INT (immediate);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-(define_insn_and_split "*xxspltidp_<mode>_internal"
- [(set (match_operand:XXSPLTIDP_V 0 "vsx_register_operand" "=wa")
- (match_operand:XXSPLTIDP_V 1 "easy_vector_constant_64bit_element" "eV"))]
- "TARGET_POWER10"
- "#"
- "&& 1"
- [(set (match_dup 0)
- (unspec:XXSPLTIDP_V [(match_dup 2)] UNSPEC_XXSPLTIDP))]
-{
- long immediate = xxspltidp_constant_immediate (operands[1], <MODE>mode);
- operands[2] = GEN_INT (immediate);
-}
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
;; XXSPLTI32DX built-in function support
(define_expand "xxsplti32dx_v4si"
[(set (match_operand:V4SI 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index 4ad0e745c94..2b41cb7fb7b 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,21 +3333,9 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eF
-A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction.
-
@item eI
A signed 34-bit integer constant if prefixed instructions are supported.
-@item eQ
-An IEEE 128-bit constant that can be loaded with the LXVKQ instruction.
-
-@item eV
-A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction.
-
-@item eW
-A vector constant that can be loaded with the XXSPLTIW instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c
deleted file mode 100644
index 23ee7e85d84..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c
+++ /dev/null
@@ -1,144 +0,0 @@
-/* { dg-require-effective-target ppc_float128_hw } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */
-
-/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit
- constants. */
-
-_Float128
-return_0 (void)
-{
- return 0.0f128; /* XXSPLTIB 34,0. */
-}
-
-_Float128
-return_1 (void)
-{
- return 1.0f128; /* LXVKQ 34,1. */
-}
-
-_Float128
-return_2 (void)
-{
- return 2.0f128; /* LXVKQ 34,2. */
-}
-
-_Float128
-return_3 (void)
-{
- return 3.0f128; /* LXVKQ 34,3. */
-}
-
-_Float128
-return_4 (void)
-{
- return 4.0f128; /* LXVKQ 34,4. */
-}
-
-_Float128
-return_5 (void)
-{
- return 5.0f128; /* LXVKQ 34,5. */
-}
-
-_Float128
-return_6 (void)
-{
- return 6.0f128; /* LXVKQ 34,6. */
-}
-
-_Float128
-return_7 (void)
-{
- return 7.0f128; /* LXVKQ 34,7. */
-}
-
-_Float128
-return_m0 (void)
-{
- return -0.0f128; /* LXVKQ 34,16. */
-}
-
-_Float128
-return_m1 (void)
-{
- return -1.0f128; /* LXVKQ 34,17. */
-}
-
-_Float128
-return_m2 (void)
-{
- return -2.0f128; /* LXVKQ 34,18. */
-}
-
-_Float128
-return_m3 (void)
-{
- return -3.0f128; /* LXVKQ 34,19. */
-}
-
-_Float128
-return_m4 (void)
-{
- return -4.0f128; /* LXVKQ 34,20. */
-}
-
-_Float128
-return_m5 (void)
-{
- return -5.0f128; /* LXVKQ 34,21. */
-}
-
-_Float128
-return_m6 (void)
-{
- return -6.0f128; /* LXVKQ 34,22. */
-}
-
-_Float128
-return_m7 (void)
-{
- return -7.0f128; /* LXVKQ 34,23. */
-}
-
-_Float128
-return_inf (void)
-{
- return __builtin_inff128 (); /* LXVKQ 34,8. */
-}
-
-_Float128
-return_minf (void)
-{
- return - __builtin_inff128 (); /* LXVKQ 34,24. */
-}
-
-_Float128
-return_nan (void)
-{
- return __builtin_nanf128 (""); /* LXVKQ 34,9. */
-}
-
-/* Note, the following NaNs should not generate a LXVKQ instruction. */
-_Float128
-return_mnan (void)
-{
- return - __builtin_nanf128 (""); /* PLXV 34,... */
-}
-
-_Float128
-return_nan2 (void)
-{
- return __builtin_nanf128 ("1"); /* PLXV 34,... */
-}
-
-_Float128
-return_nans (void)
-{
- return __builtin_nansf128 (""); /* PLXV 34,... */
-}
-
-/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */
-/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */
-
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work070)] Revert patches.
@ 2021-10-05 21:20 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-10-05 21:20 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:726e0ed6aaa678b2410b1ea6c34a5bff75e296c0
commit 726e0ed6aaa678b2410b1ea6c34a5bff75e296c0
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 5 17:18:09 2021 -0400
Revert patches.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v2di-2.c: New test.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-df-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-di-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di-2.c: New test.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
Diff:
---
.../gcc.target/powerpc/vec-splat-constant-df-2.c | 24 --------
.../gcc.target/powerpc/vec-splat-constant-df.c | 60 -------------------
.../gcc.target/powerpc/vec-splat-constant-di-2.c | 38 ------------
.../gcc.target/powerpc/vec-splat-constant-di.c | 70 ----------------------
.../gcc.target/powerpc/vec-splat-constant-sf.c | 60 -------------------
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ---------
.../gcc.target/powerpc/vec-splat-constant-v2df-2.c | 24 --------
.../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 --------------------
.../gcc.target/powerpc/vec-splat-constant-v2di-2.c | 29 ---------
.../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ----------------
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ---------------------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ----------------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 -------------------
13 files changed, 626 deletions(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c
deleted file mode 100644
index 3b4b4e01d1b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx -mxxspltiw" } */
-
-#define M_PI 3.14159265358979323846
-#define SUBNORMAL 0x1p-149f
-
-/* Test generation of floating point constants with XXSPLTI32DX. */
-
-double
-df_double_pi (void)
-{
- return M_PI; /* 2x XXSPLTI32DX. */
-}
-
-/* This float subnormal cannot be loaded with XXSPLTIDP. */
-
-double
-v2df_double_denorm (void)
-{
- return SUBNORMAL; /* XXLXOR, XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
deleted file mode 100644
index 8f6e176f9af..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-double
-scalar_double_0 (void)
-{
- return 0.0; /* XXSPLTIB or XXLXOR. */
-}
-
-double
-scalar_double_1 (void)
-{
- return 1.0; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-double
-scalar_double_m0 (void)
-{
- return -0.0; /* XXSPLTIDP. */
-}
-
-double
-scalar_double_nan (void)
-{
- return __builtin_nan (""); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_inf (void)
-{
- return __builtin_inf (); /* XXSPLTIDP. */
-}
-
-double
-scalar_double_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inf ();
-}
-#endif
-
-double
-scalar_double_pi (void)
-{
- return M_PI; /* PLFD. */
-}
-
-double
-scalar_double_denorm (void)
-{
- return 0x1p-149f; /* PLFD. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c
deleted file mode 100644
index 30ad33388e8..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx -mxxspltiw" } */
-
-/* Test generation of integer constants loaded into the vector registers with
- the ISA 3.1 (power10) instruction XXSPLTI32DX. We use asm to force the
- value into vector registers. */
-
-#define LARGE_BITS 0x12345678ABCDEF01LL
-#define SUBNORMAL 0x8000000000000001LL
-
-/* 0x8000000000000001LL is the bit pattern for a negative subnormal value can
- be generated with XXSPLTI32DX but not XXSLTIDP. */
-double
-scalar_float_subnormal (void)
-{
- /* 2x XXSPLTI32DX. */
- double d;
- long long ll = SUBNORMAL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x12345678ABCDEF01LL is a large constant that can be loaded with 2x
- XXSPLTI32DX instructions. */
-double
-scalar_large_constant (void)
-{
- /* 2x XXSPLTI32DX. */
- double d;
- long long ll = LARGE_BITS;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
deleted file mode 100644
index 75714d0b11d..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating DImode constants that have the same bit pattern as DFmode
- constants that can be loaded with the XXSPLTIDP instruction with the ISA 3.1
- (power10). We use asm to force the value into vector registers. */
-
-double
-scalar_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- double d;
- long long ll = 0;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-double
-scalar_1 (void)
-{
- /* VSPLTISW/VUPKLSW or XXSPLTIB/VEXTSB2D. */
- double d;
- long long ll = 1;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTIDP. */
-double
-scalar_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x8000000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTIDP. */
-double
-scalar_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- double d;
- long long ll = 0x3ff0000000000000LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-double
-scalar_pi (void)
-{
- /* PLXV. */
- double d;
- long long ll = 0x400921fb54442d18LL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
deleted file mode 100644
index 72504bdfbbd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-float
-scalar_float_0 (void)
-{
- return 0.0f; /* XXSPLTIB or XXLXOR. */
-}
-
-float
-scalar_float_1 (void)
-{
- return 1.0f; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-float
-scalar_float_m0 (void)
-{
- return -0.0f; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_nan (void)
-{
- return __builtin_nanf (""); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_inf (void)
-{
- return __builtin_inff (); /* XXSPLTIDP. */
-}
-
-float
-scalar_float_m_inf (void) /* XXSPLTIDP. */
-{
- return - __builtin_inff ();
-}
-#endif
-
-float
-scalar_float_pi (void)
-{
- return (float)M_PI; /* XXSPLTIDP. */
-}
-
-float
-scalar_float_denorm (void)
-{
- return 0x1p-149f; /* PLFS. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c
deleted file mode 100644
index 8bc119ad41f..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx -mxxspltiw" } */
-
-#define M_PI 3.14159265358979323846
-#define SUBNORMAL 0x1p-149f
-
-/* Test generation of floating point constants with XXSPLTI32DX. */
-
-vector double
-v2df_double_pi (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector double) { M_PI, M_PI };
-}
-
-vector double
-v2df_double_denorm (void)
-{
- /* XXLXOR, XXSPLTI32DX. */
- return (vector double) { SUBNORMAL, SUBNORMAL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
deleted file mode 100644
index 82ffc86f8aa..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c
+++ /dev/null
@@ -1,64 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-#include <math.h>
-
-/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP
- instruction. */
-
-vector double
-v2df_double_0 (void)
-{
- return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */
-}
-
-vector double
-v2df_double_1 (void)
-{
- return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */
-}
-
-#ifndef __FAST_MATH__
-vector double
-v2df_double_m0 (void)
-{
- return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_nan (void)
-{
- return (vector double) { __builtin_nan (""),
- __builtin_nan ("") }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_inf (void)
-{
- return (vector double) { __builtin_inf (),
- __builtin_inf () }; /* XXSPLTIDP. */
-}
-
-vector double
-v2df_double_m_inf (void)
-{
- return (vector double) { - __builtin_inf (),
- - __builtin_inf () }; /* XXSPLTIDP. */
-}
-#endif
-
-vector double
-v2df_double_pi (void)
-{
- return (vector double) { M_PI, M_PI }; /* PLVX. */
-}
-
-vector double
-v2df_double_denorm (void)
-{
- return (vector double) { (double)0x1p-149f,
- (double)0x1p-149f }; /* PLVX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c
deleted file mode 100644
index 2730742752a..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx -mxxspltiw" } */
-
-/* Test generation of integer constants loaded into the vector registers with
- the ISA 3.1 (power10) instruction XXSPLTI32DX. */
-
-#define LARGE_BITS 0x12345678ABCDEF01LL
-#define SUBNORMAL 0x8000000000000001LL
-
-/* 0x8000000000000001LL is the bit pattern for a negative subnormal value can
- be generated with XXSPLTI32DX but not XXSLTIDP. */
-vector long long
-vector_float_subnormal (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector long long) { SUBNORMAL, SUBNORMAL };
-}
-
-/* 0x12345678ABCDEF01LL is a large constant that can be loaded with 2x
- XXSPLTI32DX instructions. */
-vector long long
-vector_large_constant (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector long long) { LARGE_BITS, LARGE_BITS };
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
deleted file mode 100644
index 4d44f943d26..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* Test generating V2DImode constants that have the same bit pattern as
- V2DFmode constants that can be loaded with the XXSPLTIDP instruction with
- the ISA 3.1 (power10). */
-
-vector long long
-vector_0 (void)
-{
- /* XXSPLTIB or XXLXOR. */
- return (vector long long) { 0LL, 0LL };
-}
-
-vector long long
-vector_1 (void)
-{
- /* XXSPLTIB and VEXTSB2D. */
- return (vector long long) { 1LL, 1LL };
-}
-
-/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated
- with XXSPLTISDP. */
-vector long long
-vector_float_neg_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL };
-}
-
-/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with
- XXSPLTISDP. */
-vector long long
-vector_float_1_0 (void)
-{
- /* XXSPLTIDP. */
- return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL };
-}
-
-/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated
- with XXSPLTIDP. */
-vector long long
-scalar_pi (void)
-{
- /* PLXV. */
- return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
* [gcc(refs/users/meissner/heads/work070)] Revert patches.
@ 2021-10-05 17:29 Michael Meissner
0 siblings, 0 replies; 6+ messages in thread
From: Michael Meissner @ 2021-10-05 17:29 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:be90bb72cf8c4dddf5a9995977b50701fa1737bb
commit be90bb72cf8c4dddf5a9995977b50701fa1737bb
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Oct 5 13:28:04 2021 -0400
Revert patches.
2021-10-05 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraint.md (eD): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): If the constant
can be loaded with XXSPLTI32DX, it is easy.
(easy_vector_constant_2insns): New predicate.
(easy_vector_constant): If the constant can be loaded with
XXSPLTI32DX, it is easy.
* config/rs6000/rs6000-protos.h (xxsplti32dx_constant_immediate):
New declaration.
* config/rs6000/rs6000.c (xxsplti32dx_constant_immediate): New
helper function.
(output_vec_const_move): If the operand can be loaded with
XXSPLTI32DX, split it.
(rs6000_output_move_128bit): Likewise.
(prefixed_xxsplti_p): Constants loaded with XXSPLTI32DX are
prefixed.
* config/rs6000/rs6000.md (movsf_hardfloat): Add support for
constants loaded with XXSPLTI32DX.
(mov<mode>_hardfloat32, FMOVE64 iterator): Likewise.
(mov<mode>_hardfloat64, FMOVE64 iterator): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
* config/rs6000/rs6000.opt (-mxxsplti32dx): New option.
* config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec.
(vsx_mov<mode>_64bit): Add support for constants loaded with
XXSPLTI32DX.
(vsx_mov<mode>_32bit): Likewise.
(XXSPLTI32DX): New mode iterator.
(splitter for XXSPLTI32DX): Add splitter for constants loaded with
XXSPLTI32DX.
(xxsplti32dx_<mode>_first): New insns.
(xxsplti32dx_<mode>_second): New insns.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eD constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-df-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-di-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2df-2.c: New test.
* gcc.target/powerpc/vec-splat-constant-v2di-2.c: New test.
2021-10-04 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patches.
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (easy_vector_constant_splat_word):
New predicate.
(easy_vector_constant): If we can use XXSPLTIW, the vector
constant is easy.
* config/rs6000/rs6000-protos.h (xxspltiw_constant_immediate): New
declaration.
* config/rs6000/rs6000.c (xxspltiw_constant_immediate): New
function.
(output_vec_const_move): Add support for loading up vector
constants with XXSPLTIW.
(prefixed_xxsplti_p): Recognize xxspltiw instructions as
prefixed.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eW constraint.
gcc/testsuite/
Revert patches.
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 11 --
gcc/config/rs6000/predicates.md | 166 ---------------------
gcc/config/rs6000/rs6000-protos.h | 2 -
gcc/config/rs6000/rs6000.c | 158 +-------------------
gcc/config/rs6000/rs6000.md | 119 ++++-----------
gcc/config/rs6000/rs6000.opt | 10 --
gcc/config/rs6000/vsx.md | 107 ++-----------
gcc/doc/md.texi | 6 -
.../gcc.target/powerpc/vec-splat-constant-df-2.c | 24 ---
.../gcc.target/powerpc/vec-splat-constant-di-2.c | 38 -----
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ----
.../gcc.target/powerpc/vec-splat-constant-v2df-2.c | 24 ---
.../gcc.target/powerpc/vec-splat-constant-v2di-2.c | 29 ----
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ---------
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 -------
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 --------
16 files changed, 49 insertions(+), 852 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index f9d1d1ab446..1700657abe9 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -213,12 +213,6 @@
"A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction."
(match_operand 0 "easy_fp_constant_64bit_scalar"))
-;; DImode, DFmode, V2DImode, V2DFmode constant that can be loaded with 2
-;; XXSPLTI32DX instruction.
-(define_constraint "eD"
- "A constant that can be loaded with a pair of XXSPLTI32DX instructions."
- (match_operand 0 "easy_vector_constant_2insns"))
-
;; 34-bit signed integer constant
(define_constraint "eI"
"A signed 34-bit integer constant if prefixed instructions are supported."
@@ -234,11 +228,6 @@
"An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
(match_operand 0 "easy_fp_constant_ieee128"))
-;; Vector constant that can be loaded with XXSPLTIW
-(define_constraint "eW"
- "A vector constant that can be loaded with the XXSPLTIW instruction."
- (match_operand 0 "easy_vector_constant_splat_word"))
-
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index c8f0d62d75b..30e89ec79f0 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -611,11 +611,6 @@
if (easy_fp_constant_ieee128 (op, mode))
return 1;
- /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can be
- loaded with a pair of instructions. */
- if (easy_vector_constant_2insns (op, mode))
- return 1;
-
/* Otherwise consider floating point constants hard, so that the
constant gets pushed to memory during the early RTL phases. This
has the advantage that double precision constants that can be
@@ -756,161 +751,6 @@
return easy_fp_constant_64bit_scalar (op, GET_MODE_INNER (mode));
})
-;; Return 1 if the operand is either a DImode/DFmode scalar constant or
-;; V2DImode/V2DFmode vector constant that needs 2 XXSPLTI32DX instructions to
-;; load the value
-
-(define_predicate "easy_vector_constant_2insns"
- (match_code "const_vector,vec_duplicate,const_int,const_double")
-{
- /* Can we do the XXSPLTI32DX instruction? */
- if (!TARGET_XXSPLTI32DX || !TARGET_PREFIXED || !TARGET_VSX)
- return false;
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- /* Convert vector constant/duplicate into a scalar. */
- if (CONST_VECTOR_P (op))
- {
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- op = CONST_VECTOR_ELT (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- {
- op = XEXP (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- if (GET_MODE_SIZE (mode) > 8)
- return false;
-
- /* 0.0 or 0 is easy to generate. */
- if (op == CONST0_RTX (mode))
- return false;
-
- /* If we can load up the constant in other ways (either a single load
- constant and a direct move or XXSPLTIDP), don't generate the
- XXSPLTI32DX. */
- if (CONST_INT_P (op))
- return !(satisfies_constraint_I (op)
- || satisfies_constraint_L (op)
- || satisfies_constraint_eI (op)
- || easy_fp_constant_64bit_scalar (op, mode));
-
- /* For floating point, if we can use XXSPLTIDP, we don't want to
- generate XXSPLTI32DX's. */
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- return !easy_fp_constant_64bit_scalar (op, mode);
-
- return false;
-})
-
-;; Return 1 if the operand is a constant that can be loaded with the XXSPLTIW
-;; instruction that loads up a 32-bit immediate and splats it into the vector.
-
-(define_predicate "easy_vector_constant_splat_word"
- (match_code "const_vector")
-{
- HOST_WIDE_INT value;
-
- if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTIW)
- return false;
-
- if (!CONST_VECTOR_P (op))
- return true;
-
- rtx element0 = CONST_VECTOR_ELT (op, 0);
-
- switch (mode)
- {
- /* V4SImode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V4SImode:
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- /* Don't return true if we can use the shorter vspltisw instruction. */
- value = INTVAL (element0);
- return (!EASY_VECTOR_15 (value));
-
- /* V4SFmode constant vectors that have the same element are
- can be used with XXSPLTIW. */
- case V4SFmode:
- if (!CONST_VECTOR_DUPLICATE_P (op))
- return false;
-
- /* Don't return true for 0.0f, since that can be created with
- xxspltib or xxlxor. */
- return (element0 != CONST0_RTX (SFmode));
-
- /* V8Hmode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case V8HImode:
- if (CONST_VECTOR_DUPLICATE_P (op))
- {
- /* Don't return true if we can use the shorter vspltish instruction. */
- value = INTVAL (element0);
- if (EASY_VECTOR_15 (value))
- return false;
-
- return true;
- }
-
- else
- {
- /* Check if all even elements are the same and all odd elements are
- the same. */
- rtx element1 = CONST_VECTOR_ELT (op, 1);
-
- if (!CONST_INT_P (element1))
- return false;
-
- for (size_t i = 2; i < GET_MODE_NUNITS (V8HImode); i += 2)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1)))
- return false;
-
- return true;
- }
-
- /* V16QI constant vectors that have the first four elements identical to
- the next set of 4 elements, and so forth can generate XXSPLTIW. */
- case V16QImode:
- {
- /* If we can use XXSPLTIB, don't generate XXSPLTIW. */
- if (xxspltib_constant_nosplit (op, mode))
- return false;
-
- rtx element1 = CONST_VECTOR_ELT (op, 1);
- rtx element2 = CONST_VECTOR_ELT (op, 2);
- rtx element3 = CONST_VECTOR_ELT (op, 3);
-
- if (!CONST_INT_P (element0) || !CONST_INT_P (element1)
- || !CONST_INT_P (element2) || !CONST_INT_P (element3))
- return false;
-
- for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4)
- if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1))
- || !rtx_equal_p (element2, CONST_VECTOR_ELT (op, i + 2))
- || !rtx_equal_p (element3, CONST_VECTOR_ELT (op, i + 3)))
- return false;
-
- return true;
- }
-
- default:
- break;
- }
-
- return false;
-})
-
;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB
;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction.
@@ -1031,12 +871,6 @@
if (easy_vector_constant_64bit_element (op, mode))
return true;
- if (easy_vector_constant_splat_word (op, mode))
- return true;
-
- if (easy_vector_constant_2insns (op, mode))
- return 1;
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (op, mode, &num_insns, &value))
return true;
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index f517624cc56..a21fa08b367 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -32,9 +32,7 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int,
extern int easy_altivec_constant (rtx, machine_mode);
extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *);
-extern void xxsplti32dx_constant_immediate (rtx, machine_mode, long *, long *);
extern long xxspltidp_constant_immediate (rtx, machine_mode);
-extern long xxspltiw_constant_immediate (rtx, machine_mode);
extern int lxvkq_constant_immediate (rtx, machine_mode);
extern int vspltis_shifted (rtx);
extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int);
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index f5ca8eb1703..81004d9a879 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6939,6 +6939,11 @@ xxspltib_constant_p (rtx op,
else if (IN_RANGE (value, -1, 0))
*num_insns_ptr = 1;
+ /* See if we could generate the constant with XXSPLTIW instead of XXSPLTIB +
+ VUPKLSB/VEXTSB2W. */
+ else if ((mode == V8HImode || mode == V4SImode) && TARGET_POWER10 && TARGET_XXSPLTIW)
+ return false;
+
else
*num_insns_ptr = 2;
@@ -6946,59 +6951,6 @@ xxspltib_constant_p (rtx op,
return true;
}
-/* Return the two 32-bit constants to use in the two XXSPLTI32DX instructions
- via HIGH_PTR and LOW_PTR. */
-
-void
-xxsplti32dx_constant_immediate (rtx op,
- machine_mode mode,
- long *high_ptr,
- long *low_ptr)
-{
- gcc_assert (easy_vector_constant_2insns (op, mode));
-
- if (mode == VOIDmode)
- mode = GET_MODE (op);
-
- if (CONST_VECTOR_P (op))
- {
- op = CONST_VECTOR_ELT (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- else if (GET_CODE (op) == VEC_DUPLICATE)
- {
- op = XEXP (op, 0);
- mode = GET_MODE_INNER (mode);
- }
-
- if (CONST_INT_P (op))
- {
- HOST_WIDE_INT value = INTVAL (op);
- *high_ptr = (value >> 32) & 0xffffffff;
- *low_ptr = value & 0xffffffff;
- return;
- }
-
- else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode))
- {
- long high_low[2];
- const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op);
- REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low);
-
- /* The double precision value is laid out in memory order. We need to
- undo this for XXSPLTI32DX. */
- if (!BYTES_BIG_ENDIAN)
- std::swap (high_low[0], high_low[1]);
-
- *high_ptr = high_low[0] & 0xffffffff;
- *low_ptr = high_low[1] & 0xffffffff;
- return;
- }
-
- gcc_unreachable ();
-}
-
/* Return the immediate value used in the XXSPLTIDP instruction. */
long
@@ -7053,82 +7005,6 @@ xxspltidp_constant_immediate (rtx op, machine_mode mode)
return ret;
}
-/* Return the immediate value used in the XXSPLTIW instruction. */
-long
-xxspltiw_constant_immediate (rtx op, machine_mode mode)
-{
- long ret;
-
- gcc_assert (easy_vector_constant_splat_word (op, mode));
-
- switch (mode)
- {
- default:
- gcc_unreachable ();
-
- /* V4SImode constant vectors that have the same element are can be used
- with XXSPLTIW. */
- case E_V4SImode:
- gcc_assert (CONST_VECTOR_DUPLICATE_P (op));
- ret = INTVAL (CONST_VECTOR_ELT (op, 0));
- break;
-
- /* V4SFmode constant vectors that have the same element are
- can be used with XXSPLTIW. */
- case E_V4SFmode:
- gcc_assert (CONST_VECTOR_DUPLICATE_P (op));
- ret = rs6000_const_f32_to_i32 (CONST_VECTOR_ELT (op, 0));
- break;
-
- /* V8HImode constant vectors with all of the even elements the same and
- all of the odd elements the same can used XXSPLTIW. */
- case E_V8HImode:
- {
- if (!rtx_equal_p (CONST_VECTOR_ELT (op, 0), CONST_VECTOR_ELT (op, 2))
- || !rtx_equal_p (CONST_VECTOR_ELT (op, 1), CONST_VECTOR_ELT (op, 3)))
- gcc_unreachable ();
-
- long value0 = INTVAL (CONST_VECTOR_ELT (op, 0)) & 0xffff;
- long value1 = INTVAL (CONST_VECTOR_ELT (op, 1)) & 0xffff;
-
- if (!BYTES_BIG_ENDIAN)
- std::swap (value0, value1);
-
- ret = (value0 << 16) | value1;
- }
- break;
-
- /* V16QI constant vectors that have the first four elements identical to
- the next set of 4 elements, and so forth can generate XXSPLTIW. */
- case E_V16QImode:
- {
- rtx op0 = CONST_VECTOR_ELT (op, 0);
- rtx op1 = CONST_VECTOR_ELT (op, 1);
- rtx op2 = CONST_VECTOR_ELT (op, 2);
- rtx op3 = CONST_VECTOR_ELT (op, 3);
-
- for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4)
- if (!rtx_equal_p (op0, CONST_VECTOR_ELT (op, i))
- || !rtx_equal_p (op1, CONST_VECTOR_ELT (op, i + 1))
- || !rtx_equal_p (op2, CONST_VECTOR_ELT (op, i + 2))
- || !rtx_equal_p (op3, CONST_VECTOR_ELT (op, i + 3)))
- gcc_unreachable ();
-
- long value0 = INTVAL (op0) & 0xff;
- long value1 = INTVAL (op1) & 0xff;
- long value2 = INTVAL (op2) & 0xff;
- long value3 = INTVAL (op3) & 0xff;
-
- ret = ((BYTES_BIG_ENDIAN)
- ? ((value0 << 24) | (value1 << 16) | (value2 << 8) | value3)
- : ((value3 << 24) | (value2 << 16) | (value1 << 8) | value0));
- }
- break;
- }
-
- return ret;
-}
-
/* Return the constant that will go in the LXVKQ instruction. */
/* LXVKQ immediates. */
@@ -7270,21 +7146,12 @@ output_vec_const_move (rtx *operands)
return "xxspltidp %x0,%2";
}
- if (easy_vector_constant_splat_word (vec, mode))
- {
- operands[2] = GEN_INT (xxspltiw_constant_immediate (vec, mode));
- return "xxspltiw %x0,%2";
- }
-
if (easy_fp_constant_ieee128 (vec, mode))
{
operands[2] = GEN_INT (lxvkq_constant_immediate (vec, mode));
return "lxvkq %x0,%2";
}
- if (easy_vector_constant_2insns (vec, mode))
- return "#";
-
if (TARGET_P9_VECTOR
&& xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value))
{
@@ -14133,9 +14000,6 @@ rs6000_output_move_128bit (rtx operands[])
return "lxvkq %x0,%2";
}
- else if (dest_vsx_p && easy_vector_constant_2insns (src, mode))
- return "#";
-
else if (dest_regno >= 0
&& (CONST_INT_P (src)
|| CONST_WIDE_INT_P (src)
@@ -27050,19 +26914,11 @@ prefixed_xxsplti_p (rtx_insn *insn)
case E_DImode:
case E_DFmode:
case E_SFmode:
- return (easy_fp_constant_64bit_scalar (src, mode)
- || easy_vector_constant_2insns (src, mode));
+ return easy_fp_constant_64bit_scalar (src, mode);
case E_V2DImode:
case E_V2DFmode:
- return (easy_vector_constant_64bit_element (src, mode)
- || easy_vector_constant_2insns (src, mode));
-
- case E_V16QImode:
- case E_V8HImode:
- case E_V4SImode:
- case E_V4SFmode:
- return easy_vector_constant_splat_word (src, mode);
+ return easy_vector_constant_64bit_element (src, mode);
default:
break;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 5c120ef1672..8afc4b2756d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -7764,17 +7764,17 @@
;;
;; LWZ LFS LXSSP LXSSPX STFS STXSSP
;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP
-;; MR MT<x> MF<x> NOP XXSPLTIDP XXSPLTI32DX
+;; MR MT<x> MF<x> NOP XXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa, wa")
+ !r, *c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
- r, r, *h, 0, eF, eD"))]
+ r, r, *h, 0, eF"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -7797,24 +7797,15 @@
mt%0 %1
mf%1 %0
nop
- #
#"
[(set_attr "type"
"load, fpload, fpload, fpload, fpstore, fpstore,
fpstore, store, veclogical, integer, fpsimple, fpsimple,
- *, mtjmpr, mfjmpr, *, vecperm, vecperm")
+ *, mtjmpr, mfjmpr, *, vecperm")
(set_attr "isa"
"*, *, p9v, p8v, *, p9v,
p8v, *, *, *, *, *,
- *, *, *, *, p10, p10")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, 2")])
+ *, *, *, *, p10")])
;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ
;; FMR MR MT%0 MF%1 NOP
@@ -8074,18 +8065,18 @@
;; STFD LFD FMR LXSD STXSD
;; LXSD STXSD XXLOR XXLXOR GPR<-0
-;; LWZ STW MR XXSPLTIDP XXSPLTI32DX
+;; LWZ STW MR XXSPLTIDP
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- Y, r, !r, wa, wa")
+ Y, r, !r, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
- r, Y, r, eF, eD"))]
+ r, Y, r, eF"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8103,29 +8094,20 @@
#
#
#
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, two,
- store, load, two, vecperm, vecperm")
+ store, load, two, vecperm")
(set_attr "size" "64")
(set_attr "length"
"*, *, *, *, *,
*, *, *, *, 8,
- 8, 8, 8, *, *")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
+ 8, 8, 8, *")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
- *, *, *, p10, p10")])
+ *, *, *, p10")])
;; STW LWZ MR G-const H-const F-const
@@ -8152,19 +8134,19 @@
;; STFD LFD FMR LXSD STXSD
;; LXSDX STXSDX XXLOR XXLXOR LI 0
;; STD LD MR MT{CTR,LR} MF{CTR,LR}
-;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX
+;; NOP MFVSRD MTVSRD XXSPLTIDP
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
- *h, r, <f64_dm>, wa, wa")
+ *h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
- 0, <f64_dm>, r, eF, eD"))]
+ 0, <f64_dm>, r, eF"))]
"TARGET_POWERPC64 && TARGET_HARD_FLOAT
&& (gpc_reg_operand (operands[0], <MODE>mode)
|| gpc_reg_operand (operands[1], <MODE>mode))"
@@ -8187,29 +8169,18 @@
nop
mfvsrd %0,%x1
mtvsrd %x0,%1
- #
#"
[(set_attr "type"
"fpstore, fpload, fpsimple, fpload, fpstore,
fpload, fpstore, veclogical, veclogical, integer,
store, load, *, mtjmpr, mfjmpr,
- *, mfvsr, mtvsr, vecperm, vecperm")
+ *, mfvsr, mtvsr, vecperm")
(set_attr "size" "64")
(set_attr "isa"
"*, *, *, p9v, p9v,
p7v, p7v, *, *, *,
*, *, *, *, *,
- *, p8v, p8v, p10, p10")
- (set_attr "num_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- *, *, *, *, 2")])
+ *, p8v, p8v, p10")])
;; STD LD MR MT<SPR> MF<SPR> G-const
;; H-const F-const Special
@@ -9257,7 +9228,7 @@
;; a gpr into a fpr instead of reloading an invalid 'Y' address
;; GPR store GPR load GPR move FPR store FPR load FPR move
-;; XXSPLTIDP XXSPLTI32DX
+;; XXSPLTIDP
;; GPR const AVX store AVX store AVX load AVX load VSX move
;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const
;; AVX const
@@ -9265,13 +9236,13 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=Y, r, r, m, ^d, ^d,
- ^wa, ^wa,
+ ^wa,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
"r, Y, r, ^d, m, ^d,
- eF, eD,
+ eF,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9287,7 +9258,6 @@
fmr %0,%1
#
#
- #
stxsd %1,%0
stxsdx %x1,%y0
lxsd %0,%1
@@ -9302,32 +9272,20 @@
#"
[(set_attr "type"
"store, load, *, fpstore, fpload, fpsimple,
- vecperm, vecperm,
+ vecperm,
*, fpstore, fpstore, fpload, fpload, veclogical,
vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple,
vecsimple")
(set_attr "size" "64")
(set_attr "length"
"8, 8, 8, *, *, *,
- *, *,
+ *,
16, *, *, *, *, *,
*, *, *, *, *, 8,
*")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, *,
- *")
- (set_attr "max_prefixed_insns"
- "*, *, *, *, *, *,
- *, *,
- *, *, *, *, *, *,
- *, *, *, *, *, *,
- *")
(set_attr "isa"
"*, *, *, *, *, *,
- p10, p10,
+ p10,
*, p9v, p7v, p9v, p7v, *,
p9v, p9v, p7v, *, *, p7v,
p7v")])
@@ -9363,7 +9321,7 @@
})
;; GPR store GPR load GPR move
-;; XXSPLTIDP XXSPLTI32DX
+;; XXSPLTIDP
;; GPR li GPR lis GPR pli GPR #
;; FPR store FPR load FPR move
;; AVX store AVX store AVX load AVX load VSX move
@@ -9374,7 +9332,7 @@
(define_insn "*movdi_internal64"
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
- ^wa, ^wa,
+ ^wa,
r, r, r, r,
m, ^d, ^d,
wY, Z, $v, $v, ^wa,
@@ -9384,7 +9342,7 @@
?r, ?wa")
(match_operand:DI 1 "input_operand"
"r, YZ, r,
- eF, eD,
+ eF,
I, L, eI, nF,
^d, m, ^d,
^v, $v, wY, Z, ^wa,
@@ -9400,7 +9358,6 @@
ld%U1%X1 %0,%1
mr %0,%1
#
- #
li %0,%1
lis %0,%v1
li %0,%1
@@ -9427,7 +9384,7 @@
mtvsrd %x0,%1"
[(set_attr "type"
"store, load, *,
- vecperm, vecperm,
+ vecperm,
*, *, *, *,
fpstore, fpload, fpsimple,
fpstore, fpstore, fpload, fpload, veclogical,
@@ -9438,7 +9395,7 @@
(set_attr "size" "64")
(set_attr "length"
"*, *, *,
- *, *,
+ *,
*, *, *, 20,
*, *, *,
*, *, *, *, *,
@@ -9446,29 +9403,9 @@
8, *,
*, *, *,
*, *")
- (set_attr "num_insns"
- "*, *, *,
- *, 2,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- 8, *,
- *, *, *,
- *, *")
- (set_attr "max_prefixed_insns"
- "*, *, *,
- *, 2,
- *, *, *, *,
- *, *, *,
- *, *, *, *, *,
- *, *, *, *, *,
- 8, *,
- *, *, *,
- *, *")
(set_attr "isa"
"*, *, *,
- p10, p10,
+ p10,
*, *, p10, *,
*, *, *,
p9v, p7v, p9v, p7v, *,
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 898bc4e9e6e..c9eb78952d6 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -640,20 +640,10 @@ mprivileged
Target Var(rs6000_privileged) Init(0)
Generate code that will run in privileged state.
-;; Do not enable at this time.
-mxxsplti32dx
-Target Undocumented Var(TARGET_XXSPLTI32DX) Init(0) Save
-Generate (do not generate) XXSPLTI32DX instructions.
-
mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
-;; Do not enable at this time.
-mxxspltiw
-Target Undocumented Var(TARGET_XXSPLTIW) Init(0) Save
-Generate (do not generate) XXSPLTIW instructions.
-
mlxvkq
Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index cc21c454491..d7e58654ded 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -376,7 +376,6 @@
UNSPEC_XXSPLTIW
UNSPEC_XXSPLTIDP
UNSPEC_XXSPLTI32DX
- UNSPEC_XXSPLTI32DX_CONST
UNSPEC_XXBLEND
UNSPEC_XXPERMX
])
@@ -1192,19 +1191,19 @@
;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move.
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
-;; XXSPLTIDP XXSPLTIW LXVKQ XXSPLTI32DX
+;; XXSPLTIDP LXVKQ
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
- wa, wa, wa, wa,
+ wa, wa,
?&r, ??r, ??Y, <??r>, wa, v,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
- eV, eW, eQ, eD,
+ eV, eQ,
wQ, Y, r, r, wE, jwM,
?jwM, W, <nW>, v, wZ"))]
@@ -1216,44 +1215,44 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
- vecperm, vecperm, vecperm, vecperm,
+ vecperm, vecperm,
store, load, store, *, vecsimple, vecsimple,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
- *, *, *, 2,
+ *, *,
2, 2, 2, 2, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
- *, *, *, 2,
+ *, *,
2, 2, 2, 2, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
- *, *, *, *,
+ *, *,
8, 8, 8, 8, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10, p10,
+ p10, p10,
*, *, *, *, p9v, *,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
-;; XXSPLTIDP XXSPLTIW LXVKQ XXSPLTI32DX
+;; XXSPLTIDP LXVKQ
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
- wa, wa, wa, wa,
+ wa, wa,
wa, v, ?wa, v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
- eV, eW, eQ, eD,
+ eV, eQ,
wE, jwM, ?jwM, W, <nW>,
v, wZ"))]
@@ -1265,27 +1264,17 @@
}
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
- vecperm, vecperm, vecperm, vecperm,
+ vecperm, vecperm,
vecsimple, vecsimple, vecsimple, *, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
- *, *, *, *,
+ *, *,
*, *, *, 20, 16,
*, *")
- (set_attr "num_insns"
- "*, *, *, *, *, *,
- *, *, *, 2,
- *, *, *, *, *,
- *, *")
- (set_attr "length"
- "*, *, *, *, *, *,
- *, *, *, 2,
- *, *, *, *, *,
- *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
- p10, p10, p10, p10,
+ p10, p10,
p9v, *, <VSisa>, *, *,
*, *")])
@@ -6581,74 +6570,6 @@
[(set_attr "type" "vecperm")
(set_attr "prefixed" "yes")])
-;; XXSPLTI32DX used to create 64-bit constants or vector constants where the
-;; even elements match and the odd elements match.
-(define_mode_iterator XXSPLTI32DX [DI SF DF V2DF V2DI])
-
-;; Don't split DImode before register allocation, so that it has a better
-;; chance of winding up in a GPR register.
-(define_split
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand")
- (match_operand:XXSPLTI32DX 1 "easy_vector_constant_2insns"))]
- "TARGET_POWER10 && (reload_completed || <MODE>mode != DImode)"
- [(set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 2)
- (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST))
- (set (match_dup 0)
- (unspec:XXSPLTI32DX [(match_dup 0)
- (match_dup 4)
- (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))]
-{
- long high = 0, low = 0;
-
- xxsplti32dx_constant_immediate (operands[1], <MODE>mode, &high, &low);
-
- /* If the low bits are 0 or all 1s, initialize that word first. This way we
- can use a smaller XXSPLTIB/XXLXOR/XXLORC instruction instead the first
- XXSPLTI32DX. */
- if (low == 0 || low == -1)
- {
- operands[2] = const1_rtx;
- operands[3] = GEN_INT (low);
- operands[4] = const0_rtx;
- operands[5] = GEN_INT (high);
- }
- else
- {
- operands[2] = const0_rtx;
- operands[3] = GEN_INT (high);
- operands[4] = const1_rtx;
- operands[5] = GEN_INT (low);
- }
-})
-
-;; First word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_first"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa")
- (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n")
- (match_operand 2 "const_int_operand" "O,wM,n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "@
- xxlxor %x0,%x0,%x0
- xxlorc %x0,%x0,%x0
- xxsplti32dx %x0,%1,%2"
- [(set_attr "type" "veclogical,veclogical,vecperm")
- (set_attr "prefixed" "*,*,yes")])
-
-;; Second word of XXSPLTI32DX
-(define_insn "*xxsplti32dx_<mode>_second"
- [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa")
- (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0")
- (match_operand 2 "u1bit_cint_operand" "n")
- (match_operand 3 "const_int_operand" "n")]
- UNSPEC_XXSPLTI32DX_CONST))]
- "TARGET_XXSPLTI32DX"
- "xxsplti32dx %x0,%2,%3"
- [(set_attr "type" "vecperm")
- (set_attr "prefixed" "yes")])
-
-
;; XXBLEND built-in function support
(define_insn "xxblend_<mode>"
[(set (match_operand:VM3 0 "register_operand" "=wa")
diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index feaa205291a..813d6316d8c 100644
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -3333,9 +3333,6 @@ The integer constant zero.
A constant whose negation is a signed 16-bit constant.
@end ifset
-@item eD
-A constant that can be loaded with a pair of XXSPLTI32DX instructions.
-
@item eF
A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction.
@@ -3348,9 +3345,6 @@ An IEEE 128-bit constant that can be loaded with the LXVKQ instruction.
@item eV
A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction.
-@item eW
-A vector constant that can be loaded with the XXSPLTIW instruction.
-
@ifset INTERNALS
@item G
A floating point constant that can be loaded into a register with one
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c
deleted file mode 100644
index 34ec3caa594..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx" } */
-
-#define M_PI 3.14159265358979323846
-#define SUBNORMAL 0x1p-149f
-
-/* Test generation of floating point constants with XXSPLTI32DX. */
-
-double
-df_double_pi (void)
-{
- return M_PI; /* 2x XXSPLTI32DX. */
-}
-
-/* This float subnormal cannot be loaded with XXSPLTIDP. */
-
-double
-v2df_double_denorm (void)
-{
- return SUBNORMAL; /* XXLXOR, XXSPLTI32DX. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c
deleted file mode 100644
index 41b1d703fe7..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx" } */
-
-/* Test generation of integer constants loaded into the vector registers with
- the ISA 3.1 (power10) instruction XXSPLTI32DX. We use asm to force the
- value into vector registers. */
-
-#define LARGE_BITS 0x12345678ABCDEF01LL
-#define SUBNORMAL 0x8000000000000001LL
-
-/* 0x8000000000000001LL is the bit pattern for a negative subnormal value can
- be generated with XXSPLTI32DX but not XXSLTIDP. */
-double
-scalar_float_subnormal (void)
-{
- /* 2x XXSPLTI32DX. */
- double d;
- long long ll = SUBNORMAL;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* 0x12345678ABCDEF01LL is a large constant that can be loaded with 2x
- XXSPLTI32DX instructions. */
-double
-scalar_large_constant (void)
-{
- /* 2x XXSPLTI32DX. */
- double d;
- long long ll = LARGE_BITS;
-
- __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll));
- return d;
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
deleted file mode 100644
index 2707d86e6fd..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
+++ /dev/null
@@ -1,27 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V16HI vector constants where the
- first 4 elements are the same as the next 4 elements, etc. */
-
-vector unsigned char
-v16qi_const_1 (void)
-{
- return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
- 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
-}
-
-vector unsigned char
-v16qi_const_2 (void)
-{
- return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
- 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c
deleted file mode 100644
index 3f7b0a00655..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx" } */
-
-#define M_PI 3.14159265358979323846
-#define SUBNORMAL 0x1p-149f
-
-/* Test generation of floating point constants with XXSPLTI32DX. */
-
-vector double
-v2df_double_pi (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector double) { M_PI, M_PI };
-}
-
-vector double
-v2df_double_denorm (void)
-{
- /* XXLXOR, XXSPLTI32DX. */
- return (vector double) { SUBNORMAL, SUBNORMAL };
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c
deleted file mode 100644
index 90027378012..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx" } */
-
-/* Test generation of integer constants loaded into the vector registers with
- the ISA 3.1 (power10) instruction XXSPLTI32DX. */
-
-#define LARGE_BITS 0x12345678ABCDEF01LL
-#define SUBNORMAL 0x8000000000000001LL
-
-/* 0x8000000000000001LL is the bit pattern for a negative subnormal value can
- be generated with XXSPLTI32DX but not XXSLTIDP. */
-vector long long
-vector_float_subnormal (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector long long) { SUBNORMAL, SUBNORMAL };
-}
-
-/* 0x12345678ABCDEF01LL is a large constant that can be loaded with 2x
- XXSPLTI32DX instructions. */
-vector long long
-vector_large_constant (void)
-{
- /* 2x XXSPLTI32DX. */
- return (vector long long) { LARGE_BITS, LARGE_BITS };
-}
-
-/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
deleted file mode 100644
index 05d4ee3f5cb..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SF vector constants. */
-
-vector float
-v4sf_const_1 (void)
-{
- return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_nan (void)
-{
- return (vector float) { __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf (""),
- __builtin_nanf ("") }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_inf (void)
-{
- return (vector float) { __builtin_inff (),
- __builtin_inff (),
- __builtin_inff (),
- __builtin_inff () }; /* XXSPLTIW. */
-}
-
-vector float
-v4sf_const_m0 (void)
-{
- return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
-}
-
-vector float
-v4sf_splats_1 (void)
-{
- return vec_splats (1.0f); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_nan (void)
-{
- return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
-}
-
-vector float
-v4sf_splats_inf (void)
-{
- return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
-}
-
-vector float
-v8hi_splats_m0 (void)
-{
- return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
-/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
-/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
deleted file mode 100644
index da909e948b2..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
- the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
-
-vector int
-v4si_const_1 (void)
-{
- return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
-}
-
-vector int
-v4si_const_126 (void)
-{
- return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_const_1023 (void)
-{
- return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector int
-v4si_splats_1 (void)
-{
- return vec_splats (1); /* VSLTPISW. */
-}
-
-vector int
-v4si_splats_126 (void)
-{
- return vec_splats (126); /* XXSPLTIW. */
-}
-
-vector int
-v8hi_splats_1023 (void)
-{
- return vec_splats (1023); /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
-/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
deleted file mode 100644
index 290e05d4a64..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
-
-#include <altivec.h>
-
-/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
- the power9 support (XXSPLTIB/VUPKLSB) is not done. */
-
-vector short
-v8hi_const_1 (void)
-{
- return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
-}
-
-vector short
-v8hi_const_126 (void)
-{
- return (vector short) { 126, 126, 126, 126,
- 126, 126, 126, 126 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_const_1023 (void)
-{
- return (vector short) { 1023, 1023, 1023, 1023,
- 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1 (void)
-{
- return vec_splats ((short)1); /* VSLTPISH. */
-}
-
-vector short
-v8hi_splats_126 (void)
-{
- return vec_splats ((short)126); /* XXSPLTIW. */
-}
-
-vector short
-v8hi_splats_1023 (void)
-{
- return vec_splats ((short)1023); /* XXSPLTIW. */
-}
-
-/* Test that we can optimiza V8HI where all of the even elements are the same
- and all of the odd elements are the same. */
-vector short
-v8hi_const_1023_1000 (void)
-{
- return (vector short) { 1023, 1000, 1023, 1000,
- 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
-}
-
-/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
-/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
-/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
-/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
-/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
-/* { dg-final { scan-assembler-not {\mplxv\M} } } */
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2021-10-05 23:29 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2021-10-05 21:57 [gcc(refs/users/meissner/heads/work070)] Revert patches Michael Meissner
-- strict thread matches above, loose matches on Subject: below --
2021-10-05 23:29 Michael Meissner
2021-10-05 21:49 Michael Meissner
2021-10-05 21:33 Michael Meissner
2021-10-05 21:20 Michael Meissner
2021-10-05 17:29 Michael Meissner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).