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* [gcc(refs/users/meissner/heads/work081)] Revert patch.
@ 2022-03-09 21:37 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2022-03-09 21:37 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:7f3bdc191435ee53cfaaa1f88c3a8cb9ed69e91a
commit 7f3bdc191435ee53cfaaa1f88c3a8cb9ed69e91a
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 9 16:36:58 2022 -0500
Revert patch.
2022-03-09 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
PR target/102059
* config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete.
(ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
(POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
* config/rs6000/rs6000.cc (rs6000_option_override_internal):
Delete code that set the power8 fusion options automatically.
(rs6000_opt_masks): Allow #pragma target and attribute target to set
power8-fusion and power8-fusion-sign, but these no longer represent
options that the user can set.
* config/rs6000/rs6000.h (TARGET_P8_FUSION): New macro.
(TARGET_P8_FUSION_SIGN): Likewise.
(MASK_P8_FUSION): Delete.
* config/rs6000/rs6000.opt (-mpower8-fusion): Recognize the option but
ignore the no form and warn that the option was removed for the regular
form.
(-mpower8-fusion-sign): Likewise.
* doc/invoke.texi (RS/6000 and PowerPC Options): Delete -mpower8-fusion
and -mpower8-fusion-sign.
gcc/testsuite/
Revert patch.
PR target/102059
* gcc.target/powerpc/pr102059-4.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 22 ++++++++-----
gcc/config/rs6000/rs6000.cc | 45 ++++++++++++++++++++++-----
gcc/config/rs6000/rs6000.h | 14 +--------
gcc/config/rs6000/rs6000.opt | 14 +++------
gcc/doc/invoke.texi | 13 ++++++--
gcc/testsuite/gcc.target/powerpc/pr102059-4.c | 23 --------------
6 files changed, 68 insertions(+), 63 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index a05b2d8c41a..963947f6939 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -43,7 +43,9 @@
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_VSX)
-/* For now, don't provide an embedded version of ISA 2.07. */
+/* For now, don't provide an embedded version of ISA 2.07. Do not set power8
+ fusion here, instead set it in rs6000.cc if we are tuning for a power8
+ system. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
@@ -52,14 +54,19 @@
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC)
+/* ISA masks setting fusion options. */
+#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
+ | OPTION_MASK_P8_FUSION_SIGN)
+
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
-#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
- | OPTION_MASK_ISEL \
- | OPTION_MASK_MODULO \
- | OPTION_MASK_P9_MINMAX \
- | OPTION_MASK_P9_MISC \
- | OPTION_MASK_P9_VECTOR)
+#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
+ | OPTION_MASK_ISEL \
+ | OPTION_MASK_MODULO \
+ | OPTION_MASK_P9_MINMAX \
+ | OPTION_MASK_P9_MISC \
+ | OPTION_MASK_P9_VECTOR) \
+ & ~OTHER_FUSION_MASKS)
/* Support for the IEEE 128-bit floating point hardware requires a lot of the
VSX instructions that are part of ISA 3.0. */
@@ -133,6 +140,7 @@
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
+ | OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index d47e771f4e0..3afe78f5d04 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4040,6 +4040,41 @@ rs6000_option_override_internal (bool global_init_p)
&& optimize_function_for_speed_p (cfun))
rs6000_isa_flags |= OPTION_MASK_SAVE_TOC_INDIRECT;
+ /* Enable power8 fusion if we are tuning for power8, even if we aren't
+ generating power8 instructions. Power9 does not optimize power8 fusion
+ cases. */
+ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
+ {
+ if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
+ else
+ rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
+ }
+
+ /* Setting additional fusion flags turns on base fusion. */
+ if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
+ {
+ if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
+ {
+ if (TARGET_P8_FUSION_SIGN)
+ error ("%qs requires %qs", "-mpower8-fusion-sign",
+ "-mpower8-fusion");
+
+ rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
+ }
+ else
+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
+ }
+
+ /* Power8 does not fuse sign extended loads with the addis. If we are
+ optimizing at high levels for speed, convert a sign extended load into a
+ zero extending load, and an explicit sign extension. */
+ if (TARGET_P8_FUSION
+ && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
+ && optimize_function_for_speed_p (cfun)
+ && optimize >= 3)
+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
+
/* ISA 3.0 vector instructions include ISA 2.07. */
if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
{
@@ -23948,6 +23983,8 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "pcrel-opt", OPTION_MASK_PCREL_OPT, false, true },
{ "popcntb", OPTION_MASK_POPCNTB, false, true },
{ "popcntd", OPTION_MASK_POPCNTD, false, true },
+ { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
+ { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
@@ -23987,14 +24024,6 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
#endif
{ "soft-float", OPTION_MASK_SOFT_FLOAT, false, false },
{ "string", 0, false, false },
-
- /* Power8 fusion options were removed, but ignore using them in #pragma and
- attribute target. Users may have used these options to suppress errors if
- they declare an inline function to be specifically power8 and the function
- was included by power9 or power10 which turned off the power8 fusion
- support. */
- { "power8-fusion", 0, false, true },
- { "power8-fusion-sign", 0, false, true },
};
/* Builtin mask mapping for printing the flags. */
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 4ae45ff822f..17af314416c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -504,19 +504,6 @@ extern int rs6000_vector_align[];
#define TARGET_MINMAX (TARGET_HARD_FLOAT && TARGET_PPC_GFXOPT \
&& (TARGET_P9_MINMAX || !flag_trapping_math))
-/* Power8 has special fusion operations that are enabled if we are tuning for
- power8. This used to be settable with an option (-mpower8-fusion), but that
- option has been removed. */
-#define TARGET_P8_FUSION (rs6000_tune == PROCESSOR_POWER8)
-
-/* Power8 fusion does not fuse loads with sign extends. If we are doing higher
- optimization levels, split loads with sign extension to loads with zero
- extension and an explicit sign extend operation, so that the zero extending
- load can be fused. */
-#define TARGET_P8_FUSION_SIGN (TARGET_P8_FUSION \
- && optimize_function_for_speed_p (cfun) \
- && optimize >= 3)
-
/* In switching from using target_flags to using rs6000_isa_flags, the options
machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map
OPTION_MASK_<xxx> back into MASK_<xxx>. */
@@ -530,6 +517,7 @@ extern int rs6000_vector_align[];
#define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
#define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
#define MASK_FPRND OPTION_MASK_FPRND
+#define MASK_P8_FUSION OPTION_MASK_P8_FUSION
#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
#define MASK_HTM OPTION_MASK_HTM
#define MASK_ISEL OPTION_MASK_ISEL
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index ffb63027cce..4931d781c4e 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -474,19 +474,13 @@ Save the TOC in the prologue for indirect calls rather than inline.
mvsx-timode
Target RejectNegative Undocumented Ignore
-# The -mpower8-fusion and -mpower8-fusion-sign options existed in the past, but
-# they have been removed.
-mno-power8-fusion
-Target RejectNegative Undocumented Ignore
-
mpower8-fusion
-Target RejectNegative Undocumented WarnRemoved
-
-mno-power8-fusion-sign
-Target RejectNegative Undocumented Ignore
+Target Mask(P8_FUSION) Var(rs6000_isa_flags)
+Fuse certain integer operations together for better performance on power8.
mpower8-fusion-sign
-Target RejectNegative Undocumented WarnRemoved
+Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
+Allow sign extension in fusion operations.
mpower8-vector
Target Mask(P8_VECTOR) Var(rs6000_isa_flags)
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index cf7e4e22de6..a0fa5e1cf43 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1255,7 +1255,8 @@ See RS/6000 and PowerPC Options.
-mveclibabi=@var{type} -mfriz -mno-friz @gol
-mpointers-to-nested-functions -mno-pointers-to-nested-functions @gol
-msave-toc-indirect -mno-save-toc-indirect @gol
--mpower8-vector -mno-power8-vector -mcrypto -mno-crypto -mhtm -mno-htm @gol
+-mpower8-fusion -mno-mpower8-fusion -mpower8-vector -mno-power8-vector @gol
+-mcrypto -mno-crypto -mhtm -mno-htm @gol
-mquad-memory -mno-quad-memory @gol
-mquad-memory-atomic -mno-quad-memory-atomic @gol
-mcompat-align-parm -mno-compat-align-parm @gol
@@ -28079,7 +28080,7 @@ following options:
-mpopcntb -mpopcntd -mpowerpc64 @gol
-mpowerpc-gpopt -mpowerpc-gfxopt @gol
-mmulhw -mdlmzb -mmfpgpr -mvsx @gol
--mcrypto -mhtm -mpower8-vector @gol
+-mcrypto -mhtm -mpower8-fusion -mpower8-vector @gol
-mquad-memory -mquad-memory-atomic -mfloat128 @gol
-mfloat128-hardware -mprefixed -mpcrel -mmma @gol
-mrop-protect}
@@ -28194,6 +28195,14 @@ Enable (disable) the use of the built-in functions that allow direct
access to the Hardware Transactional Memory (HTM) instructions that
were added in version 2.07 of the PowerPC ISA.
+@item -mpower8-fusion
+@itemx -mno-power8-fusion
+@opindex mpower8-fusion
+@opindex mno-power8-fusion
+Generate code that keeps (does not keeps) some integer operations
+adjacent so that the instructions can be fused together on power8 and
+later processors.
+
@item -mpower8-vector
@itemx -mno-power8-vector
@opindex mpower8-vector
diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c b/gcc/testsuite/gcc.target/powerpc/pr102059-4.c
deleted file mode 100644
index 5fe66f8af4b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-/* { dg-require-effective-target power10_ok } */
-
-/* Verify that power10 can explicity include functions compiled for power8.
- The issue was -mcpu=power8 enables -mpower8-fusion, but -mcpu=power9 or
- -mcpu=power10 do not set power8-fusion by default. Thus when doing this
- compilation, they would get an error that the inline function failed in its
- inlining due to having incompatible options. */
-
-static inline int __attribute__ ((always_inline,target("cpu=power8")))
-foo (int *b)
-{
- *b += 10;
- return *b;
-}
-
-int
-bar (int *a)
-{
- *a = foo (a);
- return 0;
-}
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Revert patch.
@ 2022-03-09 17:15 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2022-03-09 17:15 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:dc6d9598456fbb08438d6fdc953ecf1fbbadf899
commit dc6d9598456fbb08438d6fdc953ecf1fbbadf899
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 9 12:14:16 2022 -0500
Revert patch.
2022-03-09 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
PR target/102059
* config/rs6000/rs6000-cpus.def (OTHER_FUSION_MASKS): Delete.
(ISA_3_0_MASKS_SERVER): Don't clear the fusion masks.
(POWERPC_MASKS): Remove OPTION_MASK_P8_FUSION.
* config/rs6000/rs6000.cc (rs6000_option_override_internal):
Change how power8 fusion options are set from being an option mask
to being separate variables.
(rs6000_opt_masks): Remove -mpower8-fusion and
-mpower8-fusion-sign.
* config/rs6000/rs6000.h (MASK_P8_FUSION): Delete.
* config/rs6000/rs6000.opt (-mpower8-fusion): Change from being an
option mask to being a separate variable.
(-mpower8-fusion-sign): Likewise.
gcc/testsuite/
Revert patch.
PR target/102059
* gcc.target/powerpc/pr102059-4.c: New test.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 22 ++++++++++------
gcc/config/rs6000/rs6000.cc | 36 +++++++++++++++++++++------
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.opt | 4 +--
gcc/testsuite/gcc.target/powerpc/pr102059-4.c | 23 -----------------
5 files changed, 47 insertions(+), 39 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index ea15b8f812c..963947f6939 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -43,7 +43,9 @@
| OPTION_MASK_ALTIVEC \
| OPTION_MASK_VSX)
-/* For now, don't provide an embedded version of ISA 2.07. */
+/* For now, don't provide an embedded version of ISA 2.07. Do not set power8
+ fusion here, instead set it in rs6000.cc if we are tuning for a power8
+ system. */
#define ISA_2_7_MASKS_SERVER (ISA_2_6_MASKS_SERVER \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_CRYPTO \
@@ -52,14 +54,19 @@
| OPTION_MASK_QUAD_MEMORY \
| OPTION_MASK_QUAD_MEMORY_ATOMIC)
+/* ISA masks setting fusion options. */
+#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
+ | OPTION_MASK_P8_FUSION_SIGN)
+
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
-#define ISA_3_0_MASKS_SERVER (ISA_2_7_MASKS_SERVER \
- | OPTION_MASK_ISEL \
- | OPTION_MASK_MODULO \
- | OPTION_MASK_P9_MINMAX \
- | OPTION_MASK_P9_MISC \
- | OPTION_MASK_P9_VECTOR) \
+#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
+ | OPTION_MASK_ISEL \
+ | OPTION_MASK_MODULO \
+ | OPTION_MASK_P9_MINMAX \
+ | OPTION_MASK_P9_MISC \
+ | OPTION_MASK_P9_VECTOR) \
+ & ~OTHER_FUSION_MASKS)
/* Support for the IEEE 128-bit floating point hardware requires a lot of the
VSX instructions that are part of ISA 3.0. */
@@ -133,6 +140,7 @@
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW \
| OPTION_MASK_NO_UPDATE \
+ | OPTION_MASK_P8_FUSION \
| OPTION_MASK_P8_VECTOR \
| OPTION_MASK_P9_MINMAX \
| OPTION_MASK_P9_MISC \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index cb27b1bee05..3afe78f5d04 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -4043,17 +4043,37 @@ rs6000_option_override_internal (bool global_init_p)
/* Enable power8 fusion if we are tuning for power8, even if we aren't
generating power8 instructions. Power9 does not optimize power8 fusion
cases. */
- if (!OPTION_SET_P (TARGET_P8_FUSION))
- TARGET_P8_FUSION = (processor_target_table[tune_index].processor
- == PROCESSOR_POWER8);
+ if (!(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION))
+ {
+ if (processor_target_table[tune_index].processor == PROCESSOR_POWER8)
+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
+ else
+ rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
+ }
+
+ /* Setting additional fusion flags turns on base fusion. */
+ if (!TARGET_P8_FUSION && TARGET_P8_FUSION_SIGN)
+ {
+ if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
+ {
+ if (TARGET_P8_FUSION_SIGN)
+ error ("%qs requires %qs", "-mpower8-fusion-sign",
+ "-mpower8-fusion");
+
+ rs6000_isa_flags &= ~OPTION_MASK_P8_FUSION;
+ }
+ else
+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION;
+ }
/* Power8 does not fuse sign extended loads with the addis. If we are
optimizing at high levels for speed, convert a sign extended load into a
zero extending load, and an explicit sign extension. */
- if (!OPTION_SET_P (TARGET_P8_FUSION_SIGN))
- TARGET_P8_FUSION_SIGN = (TARGET_P8_FUSION
- && optimize_function_for_speed_p (cfun)
- && optimize >= 3);
+ if (TARGET_P8_FUSION
+ && !(rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION_SIGN)
+ && optimize_function_for_speed_p (cfun)
+ && optimize >= 3)
+ rs6000_isa_flags |= OPTION_MASK_P8_FUSION_SIGN;
/* ISA 3.0 vector instructions include ISA 2.07. */
if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
@@ -23963,6 +23983,8 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "pcrel-opt", OPTION_MASK_PCREL_OPT, false, true },
{ "popcntb", OPTION_MASK_POPCNTB, false, true },
{ "popcntd", OPTION_MASK_POPCNTD, false, true },
+ { "power8-fusion", OPTION_MASK_P8_FUSION, false, true },
+ { "power8-fusion-sign", OPTION_MASK_P8_FUSION_SIGN, false, true },
{ "power8-vector", OPTION_MASK_P8_VECTOR, false, true },
{ "power9-minmax", OPTION_MASK_P9_MINMAX, false, true },
{ "power9-misc", OPTION_MASK_P9_MISC, false, true },
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 686d7a473e0..17af314416c 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -517,6 +517,7 @@ extern int rs6000_vector_align[];
#define MASK_FLOAT128_KEYWORD OPTION_MASK_FLOAT128_KEYWORD
#define MASK_FLOAT128_HW OPTION_MASK_FLOAT128_HW
#define MASK_FPRND OPTION_MASK_FPRND
+#define MASK_P8_FUSION OPTION_MASK_P8_FUSION
#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
#define MASK_HTM OPTION_MASK_HTM
#define MASK_ISEL OPTION_MASK_ISEL
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 3327bbb2194..4931d781c4e 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -475,11 +475,11 @@ mvsx-timode
Target RejectNegative Undocumented Ignore
mpower8-fusion
-Target Var(TARGET_P8_FUSION)
+Target Mask(P8_FUSION) Var(rs6000_isa_flags)
Fuse certain integer operations together for better performance on power8.
mpower8-fusion-sign
-Target Undocumented Var(TARGET_P8_FUSION_SIGN)
+Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags)
Allow sign extension in fusion operations.
mpower8-vector
diff --git a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c b/gcc/testsuite/gcc.target/powerpc/pr102059-4.c
deleted file mode 100644
index 5fe66f8af4b..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr102059-4.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/* { dg-do compile } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-/* { dg-require-effective-target power10_ok } */
-
-/* Verify that power10 can explicity include functions compiled for power8.
- The issue was -mcpu=power8 enables -mpower8-fusion, but -mcpu=power9 or
- -mcpu=power10 do not set power8-fusion by default. Thus when doing this
- compilation, they would get an error that the inline function failed in its
- inlining due to having incompatible options. */
-
-static inline int __attribute__ ((always_inline,target("cpu=power8")))
-foo (int *b)
-{
- *b += 10;
- return *b;
-}
-
-int
-bar (int *a)
-{
- *a = foo (a);
- return 0;
-}
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work081)] Revert patch.
@ 2022-03-09 7:00 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2022-03-09 7:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:bcacea9061863dafcde148bb79656761c79ba125
commit bcacea9061863dafcde148bb79656761c79ba125
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Mar 9 01:59:43 2022 -0500
Revert patch.
2022-03-09 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
PR target/103109
* config/rs6000/rs6000.md (su_int32): New code attribute.
(<u>mul<mode><dmode>3): Convert from define_expand to
define_insn_and_split.
(maddld<mode>4): Add generator function.
(<u>mulditi3_<u>adddi3): New insn.
(<u>mulditi3_add_const): New insn.
(<u>mulditi3_<u>adddi3_upper): New insn.
(addti3): Convert from define_expand to define_insn_and_split.
(subti3): Likewise.
* config/rs6000/vsx.md (extendditi2): Allow on power9 systems.
Add isa attribute for the stuff that needs power10 support.
(zero_extendditi2): New insn.
gcc/testsuite/
Revert patch.
PR target/103109
* gcc.target/powerpc/pr103109.c: New test.
Diff:
---
gcc/config/rs6000/rs6000.md | 166 +++-------------------------
gcc/config/rs6000/vsx.md | 60 +---------
gcc/testsuite/gcc.target/powerpc/pr103109.c | 62 -----------
3 files changed, 23 insertions(+), 265 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index da7367ee642..fdfbc6566a5 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -676,9 +676,6 @@
(float "")
(unsigned_float "uns")])
-(define_code_attr su_int32 [(sign_extend "s32bit_cint_operand")
- (zero_extend "c32bit_cint_operand")])
-
; Various instructions that come in SI and DI forms.
; A generic w/d attribute, for things like cmpw/cmpd.
(define_mode_attr wd [(QI "b")
@@ -3202,16 +3199,13 @@
"mulhw<u> %0,%1,%2"
[(set_attr "type" "mul")])
-(define_insn_and_split "<u>mul<mode><dmode>3"
- [(set (match_operand:<DMODE> 0 "gpc_reg_operand" "=&r")
+(define_expand "<u>mul<mode><dmode>3"
+ [(set (match_operand:<DMODE> 0 "gpc_reg_operand")
(mult:<DMODE> (any_extend:<DMODE>
- (match_operand:GPR 1 "gpc_reg_operand" "r"))
+ (match_operand:GPR 1 "gpc_reg_operand"))
(any_extend:<DMODE>
- (match_operand:GPR 2 "gpc_reg_operand" "r"))))]
+ (match_operand:GPR 2 "gpc_reg_operand"))))]
"!(<MODE>mode == SImode && TARGET_POWERPC64)"
- "#"
- "&& 1"
- [(pc)]
{
rtx l = gen_reg_rtx (<MODE>mode);
rtx h = gen_reg_rtx (<MODE>mode);
@@ -3220,10 +3214,9 @@
emit_move_insn (gen_lowpart (<MODE>mode, operands[0]), l);
emit_move_insn (gen_highpart (<MODE>mode, operands[0]), h);
DONE;
-}
- [(set_attr "length" "8")])
+})
-(define_insn "maddld<mode>4"
+(define_insn "*maddld<mode>4"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "gpc_reg_operand" "r"))
@@ -3232,115 +3225,6 @@
"maddld %0,%1,%2,%3"
[(set_attr "type" "mul")])
-(define_insn_and_split "*<u>mulditi3_<u>adddi3"
- [(set (match_operand:TI 0 "gpc_reg_operand" "=&r")
- (plus:TI
- (mult:TI
- (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
- (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r"))))]
- "TARGET_MADDLD && TARGET_POWERPC64"
- "#"
- "&& 1"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx dest_hi = gen_highpart (DImode, dest);
- rtx dest_lo = gen_lowpart (DImode, dest);
- rtx op1 = operands[1];
- rtx op2 = operands[2];
- rtx op3 = operands[3];
- rtx tmp_hi, tmp_lo;
-
- if (can_create_pseudo_p ())
- {
- tmp_hi = gen_reg_rtx (DImode);
- tmp_lo = gen_reg_rtx (DImode);
- }
- else
- {
- tmp_hi = dest_hi;
- tmp_lo = dest_lo;
- }
-
- emit_insn (gen_<u>mulditi3_<u>adddi3_upper (tmp_hi, op1, op2, op3));
- emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3));
-
- if (can_create_pseudo_p ())
- {
- emit_move_insn (dest_hi, tmp_hi);
- emit_move_insn (dest_lo, tmp_lo);
- }
- DONE;
-}
- [(set_attr "length" "8")])
-
-;; Optimize 128-bit multiply with zero/sign extend and adding a constant. We
-;; force the constant into a register to generate li, maddhd, and maddld,
-;; instead of mulld, mulhd, addic, and addze. We can't combine this pattern
-;; with the pattern that handles registers, since constants don't have a sign
-;; or zero extend around them.
-(define_insn_and_split "*<u>mulditi3_add_const"
- [(set (match_operand:TI 0 "gpc_reg_operand" "=&r")
- (plus:TI
- (mult:TI
- (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
- (match_operand 3 "<su_int32>" "r")))]
- "TARGET_MADDLD && TARGET_POWERPC64
-"
- "#"
- "&& 1"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx dest_hi = gen_highpart (DImode, dest);
- rtx dest_lo = gen_lowpart (DImode, dest);
- rtx op1 = operands[1];
- rtx op2 = operands[2];
- rtx op3 = force_reg (DImode, operands[3]);
- rtx tmp_hi, tmp_lo;
-
- if (can_create_pseudo_p ())
- {
- tmp_hi = gen_reg_rtx (DImode);
- tmp_lo = gen_reg_rtx (DImode);
- }
- else
- {
- tmp_hi = dest_hi;
- tmp_lo = dest_lo;
- }
-
- emit_insn (gen_<u>mulditi3_<u>adddi3_upper (tmp_hi, op1, op2, op3));
- emit_insn (gen_maddlddi4 (tmp_lo, op1, op2, op3));
-
- if (can_create_pseudo_p ())
- {
- emit_move_insn (dest_hi, tmp_hi);
- emit_move_insn (dest_lo, tmp_lo);
- }
- DONE;
-}
- [(set_attr "length" "8")
- (set_attr "type" "mul")
- (set_attr "size" "64")])
-
-(define_insn "<u>mulditi3_<u>adddi3_upper"
- [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
- (truncate:DI
- (lshiftrt:TI
- (plus:TI
- (mult:TI
- (any_extend:TI (match_operand:DI 1 "gpc_reg_operand" "r"))
- (any_extend:TI (match_operand:DI 2 "gpc_reg_operand" "r")))
- (any_extend:TI (match_operand:DI 3 "gpc_reg_operand" "r")))
- (const_int 64))))]
- "TARGET_MADDLD && TARGET_POWERPC64"
- "maddhd<u> %0,%1,%2,%3"
- [(set_attr "type" "mul")
- (set_attr "size" "64")])
-
(define_insn "udiv<mode>3"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")
@@ -7145,19 +7029,12 @@
;; allocator from allocating registers that overlap with the inputs
;; (for example, having an input in 7,8 and an output in 6,7). We
;; also allow for the output being the same as one of the inputs.
-;;
-;; Addti3/subti3 are define_insn_and_splits instead of define_expand, to allow
-;; for combine to make things like multiply and add with extend operations.
-
-(define_insn_and_split "addti3"
- [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r")
- (plus:TI (match_operand:TI 1 "gpc_reg_operand" "r,0,r")
- (match_operand:TI 2 "reg_or_short_operand" "rn,r,0")))
- (clobber (reg:DI CA_REGNO))]
+
+(define_expand "addti3"
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (plus:TI (match_operand:TI 1 "gpc_reg_operand")
+ (match_operand:TI 2 "reg_or_short_operand")))]
"TARGET_64BIT"
- "#"
- "&& 1"
- [(pc)]
{
rtx lo0 = gen_lowpart (DImode, operands[0]);
rtx lo1 = gen_lowpart (DImode, operands[1]);
@@ -7174,19 +7051,13 @@
emit_insn (gen_adddi3_carry (lo0, lo1, lo2));
emit_insn (gen_adddi3_carry_in (hi0, hi1, hi2));
DONE;
-}
- [(set_attr "length" "8")
- (set_attr "type" "add")
- (set_attr "size" "128")])
+})
-(define_insn_and_split "subti3"
- [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,r,r")
- (minus:TI (match_operand:TI 1 "reg_or_short_operand" "rn,0,r")
- (match_operand:TI 2 "gpc_reg_operand" "r,r,0")))]
+(define_expand "subti3"
+ [(set (match_operand:TI 0 "gpc_reg_operand")
+ (minus:TI (match_operand:TI 1 "reg_or_short_operand")
+ (match_operand:TI 2 "gpc_reg_operand")))]
"TARGET_64BIT"
- "#"
- "&& 1"
- [(pc)]
{
rtx lo0 = gen_lowpart (DImode, operands[0]);
rtx lo1 = gen_lowpart (DImode, operands[1]);
@@ -7203,10 +7074,7 @@
emit_insn (gen_subfdi3_carry (lo0, lo2, lo1));
emit_insn (gen_subfdi3_carry_in (hi0, hi2, hi1));
DONE;
-}
- [(set_attr "length" "8")
- (set_attr "type" "add")
- (set_attr "size" "128")])
+})
\f
;; 128-bit logical operations expanders
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0d254de5aa6..d0fb92f5985 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5031,14 +5031,11 @@
;;
;; If the register allocator prefers to use Altivec registers on power10,
;; generate the vextsd2q instruction.
-;;
-;; We also need the GPR code for power9 so that we can optimize to use the
-;; multiply-add instructions.
(define_insn_and_split "extendditi2"
[(set (match_operand:TI 0 "register_operand" "=r,r,v,v,v")
(sign_extend:TI (match_operand:DI 1 "input_operand" "r,m,r,wa,Z")))
(clobber (reg:DI CA_REGNO))]
- "TARGET_POWERPC64 && TARGET_MADDLD"
+ "TARGET_POWERPC64 && TARGET_POWER10"
"#"
"&& reload_completed"
[(pc)]
@@ -5055,7 +5052,10 @@
rtx dest_lo = gen_lowpart (DImode, dest);
emit_move_insn (dest_lo, src);
- emit_insn (gen_ashrdi3 (dest_hi, dest_lo, GEN_INT (63)));
+ /* In case src is a MEM, we have to use the destination, which is a
+ register, instead of re-using the source. */
+ rtx src2 = (REG_P (src) || SUBREG_P (src)) ? src : dest_lo;
+ emit_insn (gen_ashrdi3 (dest_hi, src2, GEN_INT (63)));
DONE;
}
@@ -5082,7 +5082,7 @@
gcc_unreachable ();
}
[(set_attr "length" "8")
- (set_attr "isa" "p9,p9,p10,p10,p10")])
+ (set_attr "type" "shift,load,vecmove,vecperm,load")])
;; Sign extend 64-bit value in TI reg, word 1, to 128-bit value in TI reg
(define_insn "extendditi2_vector"
@@ -5093,54 +5093,6 @@
"vextsd2q %0,%1"
[(set_attr "type" "vecexts")])
-;; Zero extend DImode to TImode when the result is in GPRs or VSX registers.
-(define_insn_and_split "zero_extendditi2"
- [(set (match_operand:TI 0 "register_operand" "=r,r,wa,wa,wa")
- (zero_extend:TI (match_operand:DI 1 "input_operand" "r,m,r,wa,Z")))
- (clobber (match_scratch:DI 2 "=X,X,r,wa,X"))]
- "TARGET_POWERPC64 && TARGET_MADDLD"
- "#"
- "&& reload_completed"
- [(pc)]
-{
- rtx dest = operands[0];
- rtx src = operands[1];
- rtx tmp = operands[2];
- int dest_regno = reg_or_subregno (dest);
-
- /* Handle conversion to GPR registers. Load up the low part and then load
- 0 to clear the upper part. */
- if (INT_REGNO_P (dest_regno))
- {
- rtx dest_hi = gen_highpart (DImode, dest);
- rtx dest_lo = gen_lowpart (DImode, dest);
-
- emit_move_insn (dest_lo, src);
- emit_move_insn (dest_hi, const0_rtx);
- DONE;
- }
-
- /* For conversion to a VSX register, generate either a load rightmost
- double word instruction, or do a CONCAT operation with the upper word
- set to 0. */
- else if (VSX_REGNO_P (dest_regno))
- {
- if (MEM_P (src))
- emit_insn (gen_vsx_lxvrdx (dest, src));
- else
- {
- rtx dest_v2di = gen_rtx_REG (V2DImode, dest_regno);
- emit_move_insn (tmp, const0_rtx);
- emit_insn (gen_vsx_concat_v2di (dest_v2di, tmp, src));
- }
- DONE;
- }
-
- else
- gcc_unreachable ();
-}
- [(set_attr "length" "8")
- (set_attr "isa" "p9,p9,p9v,p9v,p10")])
\f
;; ISA 3.0 Binary Floating-Point Support
diff --git a/gcc/testsuite/gcc.target/powerpc/pr103109.c b/gcc/testsuite/gcc.target/powerpc/pr103109.c
deleted file mode 100644
index 7f67816edda..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr103109.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/* { dg-require-effective-target int128 } */
-/* { dg-require-effective-target power10_ok } */
-/* { dg-options "-mdejagnu-cpu=power10 -O2" } */
-
-/* This test makes sure that GCC generates the maddhd, maddhdu, and maddld
- power9 instructions when doing some forms of 64-bit integers converted to
- 128-bit integers and used with multiply/add operations. */
-
-__int128_t
-s_mult_add (long long a,
- long long b,
- long long c)
-{
- /* maddhd, maddld. */
- return ((__int128_t)a * (__int128_t)b) + (__int128_t)c;
-}
-
-/* Test 32-bit constants that are loaded into GPRs instead of doing the
- mulld/mulhd and then addic/addime or addc/addze. */
-__int128_t
-s_mult_add_m10 (long long a,
- long long b)
-{
- /* maddhd, maddld. */
- return ((__int128_t)a * (__int128_t)b) - 10;
-}
-
-__int128_t
-s_mult_add_70000 (long long a,
- long long b)
-{
- /* maddhd, maddld. */
- return ((__int128_t)a * (__int128_t)b) + 70000;
-}
-
-__uint128_t
-u_mult_add (unsigned long long a,
- unsigned long long b,
- unsigned long long c)
-{
- /* maddhd, maddld. */
- return ((__uint128_t)a * (__uint128_t)b) + (__uint128_t)c;
-}
-
-__uint128_t
-u_mult_add_0x80000000 (unsigned long long a,
- unsigned long long b)
-{
- /* maddhd, maddld. */
- return ((__uint128_t)a * (__uint128_t)b) + 0x80000000UL;
-}
-
-/* { dg-final { scan-assembler-not {\maddc\M} } } */
-/* { dg-final { scan-assembler-not {\madde\M} } } */
-/* { dg-final { scan-assembler-not {\maddid\M} } } */
-/* { dg-final { scan-assembler-not {\maddme\M} } } */
-/* { dg-final { scan-assembler-not {\maddze\M} } } */
-/* { dg-final { scan-assembler-not {\mmulhd\M} } } */
-/* { dg-final { scan-assembler-not {\mmulld\M} } } */
-/* { dg-final { scan-assembler-times {\mmaddhd\M} 3 } } */
-/* { dg-final { scan-assembler-times {\mmaddld\M} 3 } } */
-
^ permalink raw reply [flat|nested] 3+ messages in thread
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