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* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero extension into vsx_extract from memory with variable element.
@ 2023-04-21 4:21 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-21 4:21 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:74f840c6ceef5e2c92f31dfde9b23e41e9007be4
commit 74f840c6ceef5e2c92f31dfde9b23e41e9007be4
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 00:20:54 2023 -0400
Fold sign or zero extension into vsx_extract from memory with variable element.
This patch folds conversion to floating point of vsx_extract from memory of V4SI
elements where the element number is constant. This code optimizes things so it
will load the integer with LFIWAX or LFIWZX directly into a vector register
rather than loading it into a GPR and doing a direct move operation.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<uns><mode>): New
insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-4.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 30 ++++++++++++++++++++++
| 27 +++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3364a0791c2..457513a4eaa 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4214,6 +4214,36 @@
(set_attr "length" "12,16,16,20")
(set_attr "isa" "*,*,p9v,p9v")])
+;; Extract a V4SI element from memory with variable element number and convert
+;; it to SFmode or DFmode using either signed or unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
+ (any_float:SFDF
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))
+ (clobber (match_scratch:DI 4 "=f,v"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (float:SFDF (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "20")
+ (set_attr "isa" "*,p8v")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
new file mode 100644
index 00000000000..415dee36d8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and convert the value to float, and double by loading the value
+ directly into a vector register, and not loading up the GPRs first. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+float
+extract_float_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero extension into vsx_extract from memory with variable element.
@ 2023-04-21 15:40 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-21 15:40 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:11d2085d9127b313e2898ded2bd4fa355487dc0e
commit 11d2085d9127b313e2898ded2bd4fa355487dc0e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 11:40:33 2023 -0400
Fold sign or zero extension into vsx_extract from memory with variable element.
This patch folds conversion to floating point of vsx_extract from memory of V4SI
elements where the element number is constant. This code optimizes things so it
will load the integer with LFIWAX or LFIWZX directly into a vector register
rather than loading it into a GPR and doing a direct move operation.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<uns><mode>): New
insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-4.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 30 ++++++++++++++++++++++
| 27 +++++++++++++++++++
2 files changed, 57 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3364a0791c2..457513a4eaa 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4214,6 +4214,36 @@
(set_attr "length" "12,16,16,20")
(set_attr "isa" "*,*,p9v,p9v")])
+;; Extract a V4SI element from memory with variable element number and convert
+;; it to SFmode or DFmode using either signed or unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
+ (any_float:SFDF
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))
+ (clobber (match_scratch:DI 4 "=f,v"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (float:SFDF (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "20")
+ (set_attr "isa" "*,p8v")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
new file mode 100644
index 00000000000..415dee36d8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and convert the value to float, and double by loading the value
+ directly into a vector register, and not loading up the GPRs first. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+float
+extract_float_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Fold sign or zero extension into vsx_extract from memory with variable element.
@ 2023-04-21 15:35 Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2023-04-21 15:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9e52adf2cb3b591b176548c68fd15a70bd42b530
commit 9e52adf2cb3b591b176548c68fd15a70bd42b530
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 11:33:12 2023 -0400
Fold sign or zero extension into vsx_extract from memory with variable element.
This patch folds conversion to floating point of vsx_extract from memory of V4SI
elements where the element number is constant. This code optimizes things so it
will load the integer with LFIWAX or LFIWZX directly into a vector register
rather than loading it into a GPR and doing a direct move operation.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<uns><mode>): New
insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: Updated.
* gcc.target/powerpc/vec-extract-mem-int-4.c: Updated.
Diff:
---
gcc/config/rs6000/vsx.md | 30 ++++++++++++++++++++++
| 5 +++-
| 27 +++++++++++++++++++
3 files changed, 61 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 3364a0791c2..457513a4eaa 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4214,6 +4214,36 @@
(set_attr "length" "12,16,16,20")
(set_attr "isa" "*,*,p9v,p9v")])
+;; Extract a V4SI element from memory with variable element number and convert
+;; it to SFmode or DFmode using either signed or unsigned conversion.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<uns><mode>"
+ [(set (match_operand:SFDF 0 "register_operand" "=wa,wa")
+ (any_float:SFDF
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))
+ (clobber (match_scratch:DI 4 "=f,v"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_POWERPC64"
+ "#"
+ "&& 1"
+ [(set (match_dup 4)
+ (match_dup 5))
+ (set (match_dup 0)
+ (float:SFDF (match_dup 4)))]
+{
+ if (GET_CODE (operands[4]) == SCRATCH)
+ operands[4] = gen_reg_rtx (DImode);
+
+ rtx new_mem = rs6000_adjust_vec_address (operands[4], operands[1], operands[2],
+ operands[3], SImode);
+ operands[5] = gen_rtx_<SIGN_ZERO_EXTEND> (DImode, new_mem);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "20")
+ (set_attr "isa" "*,p8v")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index 437001a6177..17db9bbe107 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -22,5 +22,8 @@ extract_uns_v4si_var (vector unsigned int *p, size_t n)
/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
-/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
/* { dg-final { scan-assembler-not {\mextsw\M} } } */
+
+/* There are 2 rldicl's to make the variable element number, but there is not a
+ third one to do the zero extension. */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
new file mode 100644
index 00000000000..415dee36d8a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-4.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and convert the value to float, and double by loading the value
+ directly into a vector register, and not loading up the GPRs first. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+float
+extract_float_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfiwax or lxsiwax. */
+}
+
+double
+extract_double_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfiwzx or lxsiwzx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfiwax\M|\mlxsiwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlfiwzx\M|\mlxsiwzx\M} 1 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mmtvsrw[sz]\M} } } */
^ permalink raw reply [flat|nested] 3+ messages in thread
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