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* [gcc(refs/users/meissner/heads/work119)] Improve vec_extract of V4SF with variable element number.
@ 2023-04-21 19:49 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-21 19:49 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:9675ccd544a0d07d4e319181cde1a88c7dac3f26
commit 9675ccd544a0d07d4e319181cde1a88c7dac3f26
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 15:49:24 2023 -0400
Improve vec_extract of V4SF with variable element number.
This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
where the element number is variable combined with a conversion to DFmode.
In addition, I changed the vec_extract of V4SFmode where the element number is
variable without conversion to do the split before register allocation. I also
set the length attribute for the length before the split is done.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
register allocation.
(vsx_extract_v4sf_var_load_to_df): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-float-2.c: New test.
Diff:
---
gcc/config/rs6000/vsx.md | 31 ++++++++++++++++++----
| 28 +++++++++++++++++++
2 files changed, 54 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c3848de5d4f..ea29df72ccc 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3607,22 +3607,43 @@
DONE;
})
-;; Variable V4SF extract from memory
+;; V4SF extract from memory with variable element number.
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+ (clobber (match_scratch:P 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,load")])
+ [(set_attr "type" "fpload,load")
+ (set_attr "length" "12")])
+
+;; V4SF extract from memory and convert to DFmode with variable element number.
+(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+ (float_extend:DF
+ (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:P 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode)"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (float_extend:DF (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SFmode);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
new file mode 100644
index 00000000000..a621e45e1ad
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
@@ -0,0 +1,28 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ float (SF) variables directly using a single LFSX or LXSSPX instruction.
+ This includes loading a float and converting it to double. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+float
+extract_float_var (vector float *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfsx or lxsspx. */
+}
+
+double
+extract_float_to_double_var (vector float *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfsx or lxsspx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfsx\M|\{mlxsspx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlxv\M|\mlxvx\M} } } */
+/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */
+/* { dg-final { scan-assembler-not {\mvslo\M} } } */
+/* { dg-final { scan-assembler-not {\mxscvspdp\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Improve vec_extract of V4SF with variable element number.
@ 2023-04-21 22:01 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-21 22:01 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b356c9b29a749d29281daa1ebfd973ea69c3271b
commit b356c9b29a749d29281daa1ebfd973ea69c3271b
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 18:00:51 2023 -0400
Improve vec_extract of V4SF with variable element number.
This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
where the element number is variable combined with a conversion to DFmode.
I also modified the insn for vec_extract of V4SFmode where the element number is
variable to split before register allocation.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
register allocation.
(vsx_extract_v4sf_var_load_to_df): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-float-2.c: New test.
Diff:
---
gcc/config/rs6000/vsx.md | 21 ++++++++++++++++++-
| 24 ++++++++++++++++++++++
2 files changed, 44 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 17e56ab1ce4..1141e7b9fa7 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3616,7 +3616,7 @@
(clobber (match_scratch:DI 3 "=&b,&b"))]
"VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3624,6 +3624,25 @@
}
[(set_attr "type" "fpload,load")])
+;; V4SF extract from memory with variable element number and convert to DFmode.
+(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+ (float_extend:DF
+ (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (float_extend:DF (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SFmode);
+}
+ [(set_attr "type" "fpload")])
+
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
[(match_operand:VSX_L 0 "vsx_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
new file mode 100644
index 00000000000..65107ee0c74
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ float (SF) variables into a GPR without doing a LFS or STFS. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+void
+extract_float_0_gpr (vector float *p, float *q, size_t n)
+{
+ float x = vec_extract (*p, n);
+ __asm__ ("# %0" : "+r" (x)); /* lwz. */
+ *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M} 1 } } */
+/* { dg-final { scan-assembler-not {\mlfs\M|\mlxsspx?\M} } } */
+/* { dg-final { scan-assembler-not {\mstfs\M|\mstxsspx?\M} } } */
+/* { dg-final { scan-assembler-not {\mm[tf]vsd} } } */
+/* { dg-final { scan-assembler-not {\mxscvdpspn?\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Improve vec_extract of V4SF with variable element number.
@ 2023-04-21 20:18 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-21 20:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:27c12158404884235ba14591502b90d05c3388fa
commit 27c12158404884235ba14591502b90d05c3388fa
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 16:18:09 2023 -0400
Improve vec_extract of V4SF with variable element number.
This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
where the element number is variable combined with a conversion to DFmode.
In addition, I changed the vec_extract of V4SFmode where the element number is
variable without conversion to do the split before register allocation. I also
set the length attribute for the length before the split is done.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
register allocation.
(vsx_extract_v4sf_var_load_to_df): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-float-2.c: New test.
Diff:
---
gcc/config/rs6000/vsx.md | 25 ++++++++++++++++--
| 30 ++++++++++++++++++++++
2 files changed, 53 insertions(+), 2 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c3848de5d4f..4eba8c5ebef 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3607,7 +3607,7 @@
DONE;
})
-;; Variable V4SF extract from memory
+;; V4SF extract from memory with variable element number.
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
@@ -3622,7 +3622,28 @@
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,load")])
+ [(set_attr "type" "fpload,load")
+ (set_attr "length" "12")])
+
+;; V4SF extract from memory and convert to DFmode with variable element number.
+(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+ (float_extend:DF
+ (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (float_extend:DF (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SFmode);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
new file mode 100644
index 00000000000..7070bd24265
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
@@ -0,0 +1,30 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ float (SF) variables directly using a single LFSX or LXSSPX instruction.
+ This includes loading a float and converting it to double. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+extern vector float global;
+
+float
+extract_float_var (size_t n)
+{
+ return vec_extract (global, n); /* lfsx or lxsspx. */
+}
+
+double
+extract_float_to_double_var (size_t n)
+{
+ return vec_extract (global, n); /* lfsx or lxsspx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfsx\M|\{mlxsspx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlxv\M|\mlxvx\M} } } */
+/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */
+/* { dg-final { scan-assembler-not {\mvslo\M} } } */
+/* { dg-final { scan-assembler-not {\mxscvspdp\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Improve vec_extract of V4SF with variable element number.
@ 2023-04-21 19:35 Michael Meissner
0 siblings, 0 replies; 4+ messages in thread
From: Michael Meissner @ 2023-04-21 19:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:d39233a0c7fc59c314e54fbacba3d8018e0fc7ba
commit d39233a0c7fc59c314e54fbacba3d8018e0fc7ba
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 21 15:35:09 2023 -0400
Improve vec_extract of V4SF with variable element number.
This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
where the element number is variable combined with a conversion to DFmode.
In addition, I changed the vec_extract of V4SFmode where the element number is
variable without conversion to do the split before register allocation. I also
set the length attribute for the length before the split is done.
2023-04-21 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before
register allocation.
(vsx_extract_v4sf_var_load_to_df): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-float-2.c: New test.
Diff:
---
gcc/config/rs6000/vsx.md | 31 ++++++++++++++++++----
| 27 +++++++++++++++++++
2 files changed, 53 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index c3848de5d4f..ea29df72ccc 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3607,22 +3607,43 @@
DONE;
})
-;; Variable V4SF extract from memory
+;; V4SF extract from memory with variable element number.
(define_insn_and_split "*vsx_extract_v4sf_var_load"
[(set (match_operand:SF 0 "gpc_reg_operand" "=wa,?r")
(unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q,Q")
(match_operand:DI 2 "gpc_reg_operand" "r,r")]
UNSPEC_VSX_EXTRACT))
- (clobber (match_scratch:DI 3 "=&b,&b"))]
- "VECTOR_MEM_VSX_P (V4SFmode) && TARGET_DIRECT_MOVE_64BIT"
+ (clobber (match_scratch:P 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode)"
"#"
- "&& reload_completed"
+ "&& 1"
[(set (match_dup 0) (match_dup 4))]
{
operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
operands[3], SFmode);
}
- [(set_attr "type" "fpload,load")])
+ [(set_attr "type" "fpload,load")
+ (set_attr "length" "12")])
+
+;; V4SF extract from memory and convert to DFmode with variable element number.
+(define_insn_and_split "*vsx_extract_v4sf_var_load_to_df"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=wa")
+ (float_extend:DF
+ (unspec:SF [(match_operand:V4SF 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:P 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SFmode)"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (float_extend:DF (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+ operands[3], SFmode);
+}
+ [(set_attr "type" "fpload")
+ (set_attr "length" "12")])
;; Expand the builtin form of xxpermdi to canonical rtl.
(define_expand "vsx_xxpermdi_<mode>"
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
new file mode 100644
index 00000000000..af66fd20c21
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-2.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ float (SF) variables directly using a single LFSX or LXSSPX instruction. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+float
+extract_float_var (vector float *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfsx or lxsspx. */
+}
+
+double
+extract_float_to_double_var (vector float *p, size_t n)
+{
+ return vec_extract (*p, n); /* lfsx or lxsspx. */
+}
+
+/* { dg-final { scan-assembler-times {\mlfsx\M|\{mlxsspx\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlxv\M|\mlxvx\M} } } */
+/* { dg-final { scan-assembler-not {\mm[tf]vsr} } } */
+/* { dg-final { scan-assembler-not {\mvslo\M} } } */
+/* { dg-final { scan-assembler-not {\mxscvspdp\M} } } */
^ permalink raw reply [flat|nested] 4+ messages in thread
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