[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner]

https://gcc.gnu.org/g:63e61c4651301839e07e8e2818a174774476d8af

commit 63e61c4651301839e07e8e2818a174774476d8af
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 17:04:38 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    In addition, I changed the vec_extract of V4SFmode where the element number is
    constant without conversion to do the split before register allocation.  I also
    simplified the alternatives.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
            register allocation.
            (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-float-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 38 +++++++++++++++++-----
 .../gcc.target/powerpc/vec-extract-mem-float-1.c   | 31 ++++++++++++++++++
 2 files changed, 61 insertions(+), 8 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..17e56ab1ce4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,23 +3549,45 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
+;; V4SF extract from memory convert to DFmode with constant element number.  If
+;; the element number is 0, we don't need a temporary register.
 (define_insn_and_split "*vsx_extract_v4sf_load"
-  [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
+  [(set (match_operand:SF 0 "register_operand" "=wa,wa,?r,?r")
 	(vec_select:SF
-	 (match_operand:V4SF 1 "memory_operand" "m,Z,m,m")
-	 (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")])))
-   (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
+	 (match_operand:V4SF 1 "memory_operand" "m,Q,m,Q")
+	 (parallel
+	  [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")])))
+   (clobber (match_scratch:P 3 "=X,&b,X,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode)"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], SFmode);
 }
-  [(set_attr "type" "fpload,fpload,fpload,load")
-   (set_attr "length" "8")
-   (set_attr "isa" "*,p7v,p9v,*")])
+  [(set_attr "type" "fpload,fpload,load,load")
+   (set_attr "length" "4,8,4,8")])
+
+;; V4SF extract from memory and convert to DFmode with constant element number.
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+  [(set (match_operand:DF 0 "register_operand" "=wa,wa")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,Q")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")]))))
+   (clobber (match_scratch:P 3 "=X,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "4,8")])
 
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
new file mode 100644
index 00000000000..34ebc574339
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   float (SF) variables into a GPR without doing a LFS or STFS.  */
+
+#include <altivec.h>
+
+void
+extract_float_0_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 0);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+void
+extract_float_1_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 1);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}               2 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M}              2 } } */
+/* { dg-final { scan-assembler-not   {\mlfs\M|\mlxsspx?\M}     } } */
+/* { dg-final { scan-assembler-not   {\mstfs\M|\mstxsspx?\M}   } } */
+/* { dg-final { scan-assembler-not   {\mm[tf]vsd}              } } */
+/* { dg-final { scan-assembler-not   {\mxscvdpspn?\M}          } } */

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner]

https://gcc.gnu.org/g:bb3324da2b643fa18dacd9b6e7554e991dca0d35

commit bb3324da2b643fa18dacd9b6e7554e991dca0d35
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 15:55:18 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    In addition, I changed the vec_extract of V4SFmode where the element number is
    constant without conversion to do the split before register allocation.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
            register allocation.
            (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-float-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 24 ++++++++++++++-
 .../gcc.target/powerpc/vec-extract-mem-float-1.c   | 36 ++++++++++++++++++++++
 2 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..c3848de5d4f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,6 +3549,7 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
+;; V4SF extract from memory convert to DFmode with constant element number.
 (define_insn_and_split "*vsx_extract_v4sf_load"
   [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
 	(vec_select:SF
@@ -3557,7 +3558,7 @@
    (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode)"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3567,6 +3568,27 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
+;; V4SF extract from memory and convert to DFmode with constant element number.
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+  [(set (match_operand:DF 0 "register_operand" "=f,v,v")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,Z,m")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
+   (clobber (match_scratch:P 3 "=&b,&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p7v,p9v")])
+
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
new file mode 100644
index 00000000000..e110d308307
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   float (SF) variables into a GPR without doing a LFS or STFS.
+
+   Target LP64 and power8 vector are needed because the compiler only does the
+   vec_extract optimizations on 64-bit machines that have direct move support.
+   On earlier machines, vec_extract is done by storing the V4SF value into
+   memory, and just doing the load from memory.  */
+
+#include <altivec.h>
+
+float
+extract_float_0_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 0);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+float
+extract_float_3_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 3);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}               2 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M}              2 } } */
+/* { dg-final { scan-assembler-not   {\mlfs\M|\mlxsspx?\M}     } } */
+/* { dg-final { scan-assembler-not   {\mstfs\M|\mstxsspx?\M}   } } */
+/* { dg-final { scan-assembler-not   {\mm[tf]vsd}              } } */
+/* { dg-final { scan-assembler-not   {\mxscvdpspn?\M}          } } */

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner]

https://gcc.gnu.org/g:87ef9d86fc6fd04eb87eebc4a74b22349b7235b3

commit 87ef9d86fc6fd04eb87eebc4a74b22349b7235b3
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 15:44:03 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    In addition, I changed the vec_extract of V4SFmode where the element number is
    constant without conversion to do the split before register allocation.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
            register allocation.
            (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-float-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 24 ++++++++++++++++-
 .../gcc.target/powerpc/vec-extract-mem-float-1.c   | 31 ++++++++++++++++++++++
 2 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..c3848de5d4f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,6 +3549,7 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
+;; V4SF extract from memory convert to DFmode with constant element number.
 (define_insn_and_split "*vsx_extract_v4sf_load"
   [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
 	(vec_select:SF
@@ -3557,7 +3558,7 @@
    (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode)"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3567,6 +3568,27 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
+;; V4SF extract from memory and convert to DFmode with constant element number.
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+  [(set (match_operand:DF 0 "register_operand" "=f,v,v")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,Z,m")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
+   (clobber (match_scratch:P 3 "=&b,&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p7v,p9v")])
+
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
new file mode 100644
index 00000000000..cc10fb41894
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-O2 -mdejagnu-cpu=power8" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   float (SF) variables into a GPR without doing a LFS or STFS.  */
+
+#include <altivec.h>
+
+float
+extract_float_0_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 0);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+float
+extract_float_3_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 3);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}               2 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M}              2 } } */
+/* { dg-final { scan-assembler-not   {\mlfs\M|\mlxsspx?\M}     } } */
+/* { dg-final { scan-assembler-not   {\mstfs\M|\mstxsspx?\M}   } } */
+/* { dg-final { scan-assembler-not   {\mm[tf]vsd}              } } */
+/* { dg-final { scan-assembler-not   {\mxscvdpspn?\M}          } } */

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner]

https://gcc.gnu.org/g:5a5c396c1052046c96e5e823eee80c05ef53b0a5

commit 5a5c396c1052046c96e5e823eee80c05ef53b0a5
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 15:04:07 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    In addition, I changed the vec_extract of V4SFmode where the element number is
    constant without conversion to do the split before register allocation.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
            register allocation.
            (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-float-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 24 +++++++++++++++++-
 .../gcc.target/powerpc/vec-extract-mem-float-1.c   | 29 ++++++++++++++++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..c3848de5d4f 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,6 +3549,7 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
+;; V4SF extract from memory convert to DFmode with constant element number.
 (define_insn_and_split "*vsx_extract_v4sf_load"
   [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
 	(vec_select:SF
@@ -3557,7 +3558,7 @@
    (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode)"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3567,6 +3568,27 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
+;; V4SF extract from memory and convert to DFmode with constant element number.
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+  [(set (match_operand:DF 0 "register_operand" "=f,v,v")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,Z,m")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
+   (clobber (match_scratch:P 3 "=&b,&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p7v,p9v")])
+
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
new file mode 100644
index 00000000000..eab7892ed80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   float (SF) variables into a GPR without doing a LFS or STFS.  */
+
+#include <altivec.h>
+
+float
+extract_float_0_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 0);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+float
+extract_float_3_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 3);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}               2 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M}              2 } } */
+/* { dg-final { scan-assembler-not   {\mlfs\M|\mlxsspx?\M}     } } */
+/* { dg-final { scan-assembler-not   {\mstfs\M|\mstxsspx?\M}   } } */

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner]

https://gcc.gnu.org/g:db1da1abcc562f3f2cf109f37f4d932bff0571b9

commit db1da1abcc562f3f2cf109f37f4d932bff0571b9
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 14:57:30 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    In addition, I changed the vec_extract of V4SFmode where the element number is
    constant without conversion to do the split before register allocation.
    
    2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before
            register allocation.
            (vsx_extract_v4sf_to_df_load): New insn.
    
    gcc/testsuite/
    
            * gcc.target/powerpc/vec-extract-mem-float-1.c: New test.

Diff:
---
 gcc/config/rs6000/vsx.md                           | 24 +++++++++++++++++-
 .../gcc.target/powerpc/vec-extract-mem-float-1.c   | 29 ++++++++++++++++++++++
 2 files changed, 52 insertions(+), 1 deletion(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..84a41158d6b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3549,6 +3549,7 @@
   [(set_attr "length" "8")
    (set_attr "type" "fp")])
 
+;; V4SF extract from memory and convert to DFmode with constant element number
 (define_insn_and_split "*vsx_extract_v4sf_load"
   [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r")
 	(vec_select:SF
@@ -3557,7 +3558,7 @@
    (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))]
   "VECTOR_MEM_VSX_P (V4SFmode)"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
@@ -3567,6 +3568,27 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
+;; V4SF extract from memory and convert to DFmode with constant element number
+(define_insn_and_split "*vsx_extract_v4sf_load_to_df"
+  [(set (match_operand:DF 0 "register_operand" "=f,v,v")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,Z,m")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n")]))))
+   (clobber (match_scratch:P 3 "=&b,&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& 1"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p7v,p9v")])
+
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
new file mode 100644
index 00000000000..eab7892ed80
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-float-1.c
@@ -0,0 +1,29 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+/* { dg-options "-O2 -mvsx" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+   float (SF) variables into a GPR without doing a LFS or STFS.  */
+
+#include <altivec.h>
+
+float
+extract_float_0_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 0);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+float
+extract_float_3_gpr (vector float *p, float *q)
+{
+  float x = vec_extract (*p, 3);
+  __asm__ ("# %0" : "+r" (x));			/* lwz.  */
+  *q = x;
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M}               2 } } */
+/* { dg-final { scan-assembler-times {\mstwz\M}              2 } } */
+/* { dg-final { scan-assembler-not   {\mlfs\M|\mlxsspx?\M}     } } */
+/* { dg-final { scan-assembler-not   {\mstfs\M|\mstxsspx?\M}   } } */

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner]

https://gcc.gnu.org/g:189afb0d76cb331f3754c586133a2ea3982e1342

commit 189afb0d76cb331f3754c586133a2ea3982e1342
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 19 15:32:35 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.

Diff:
---
 gcc/config/rs6000/vsx.md | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 417aff5e24b..ebc986fc6ac 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3567,6 +3567,27 @@
    (set_attr "length" "8")
    (set_attr "isa" "*,p7v,p9v,*")])
 
+;; V4SF extract from memory and convert to DFmode with constant element number
+(define_insn_and_split "*vsx_extract_v4sf_to_df_load"
+  [(set (match_operand:DF 0 "register_operand" "=f,v")
+	(float_extend:DF
+	 (vec_select:SF
+	  (match_operand:V4SF 1 "memory_operand" "m,m")
+	  (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
+   (clobber (match_scratch:P 3 "=&b,&b"))]
+  "VECTOR_MEM_VSX_P (V4SFmode)"
+  "#"
+  "&& reload_completed"
+  [(set (match_dup 0)
+	(float_extend:DF (match_dup 4)))]
+{
+  operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
+					   operands[3], SFmode);
+}
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")
+   (set_attr "isa" "*,p8v")])
+
 ;; Variable V4SF extract from a register
 (define_insn_and_split "vsx_extract_v4sf_var"
   [(set (match_operand:SF 0 "gpc_reg_operand" "=wa")

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner]

https://gcc.gnu.org/g:354e5bb1234064a4a5a0cb88061470738107668f

commit 354e5bb1234064a4a5a0cb88061470738107668f
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 19 15:24:36 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.

Diff:
---
 gcc/config/rs6000/vsx.md | 29 ++++++++++++++++++++---------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0e681844243..c3b870640ed 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,6 +223,12 @@
 			  (V8HI  "v")
 			  (V4SI  "wa")])
 
+;; Mode attribute to give the isa constraint for accessing Altivec registers
+;; with vector extract and insert operations.
+(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
+			      (V8HI "p9v")
+			      (V4SI "p8v")])
+
 ;; Mode iterator for binary floating types other than double to
 ;; optimize convert to that floating point type from an extract
 ;; of an integer type
@@ -3951,23 +3957,28 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number.
+;; If the element number is 0, we don't need to do a load immediate operation.
+;; Likewise for GPRs with offsettable loads, we can fold the offset into the
+;; address.  For vector registers, we are limited to X-FORM memory addresses.
+;; PowerPC64 is needed because we need a DI temporary base register.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
-   (clobber (match_scratch:DI 3 "=&b"))]
-  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
+   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
+  [(set_attr "type" "load,load,load,fpload,fpload")
+   (set_attr "length" "4,4,8,4,8")
+   (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"

[gcc(refs/users/meissner/heads/work119)] Combine vec_extract of V4SF with DF convert.

[Michael Meissner]

https://gcc.gnu.org/g:2ecd33ae0e474e043aa8b509ba2bc0af1cbc8597

commit 2ecd33ae0e474e043aa8b509ba2bc0af1cbc8597
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Apr 19 15:16:48 2023 -0400

    Combine vec_extract of V4SF with DF convert.
    
    This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
    where the element number is constant combined with a conversion to DFmode.
    
    2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.

Diff:
---
 gcc/config/rs6000/vsx.md | 29 ++++++++++++++++++++---------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0e681844243..c3b870640ed 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -223,6 +223,12 @@
 			  (V8HI  "v")
 			  (V4SI  "wa")])
 
+;; Mode attribute to give the isa constraint for accessing Altivec registers
+;; with vector extract and insert operations.
+(define_mode_attr VSX_EX_ISA [(V16QI "p9v")
+			      (V8HI "p9v")
+			      (V4SI "p8v")])
+
 ;; Mode iterator for binary floating types other than double to
 ;; optimize convert to that floating point type from an extract
 ;; of an integer type
@@ -3951,23 +3957,28 @@
 }
   [(set_attr "type" "mfvsr")])
 
-;; Optimize extracting a single scalar element from memory.
+;; Extract a V16QI/V8HI/V4SI element from memory with a constant element number.
+;; If the element number is 0, we don't need to do a load immediate operation.
+;; Likewise for GPRs with offsettable loads, we can fold the offset into the
+;; address.  For vector registers, we are limited to X-FORM memory addresses.
+;; PowerPC64 is needed because we need a DI temporary base register.
 (define_insn_and_split "*vsx_extract_<mode>_load"
-  [(set (match_operand:<VEC_base> 0 "register_operand" "=r")
+  [(set (match_operand:<VEC_base> 0 "register_operand" "=r,r,r,<VSX_EX>,<VSX_EX>")
 	(vec_select:<VEC_base>
-	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m")
-	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")])))
-   (clobber (match_scratch:DI 3 "=&b"))]
-  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+	 (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m,o,m,Z,Q")
+	 (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "0,n,n,0,n")])))
+   (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+  "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_POWERPC64"
   "#"
-  "&& reload_completed"
+  "&& 1"
   [(set (match_dup 0) (match_dup 4))]
 {
   operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2],
 					   operands[3], <VEC_base>mode);
 }
-  [(set_attr "type" "load")
-   (set_attr "length" "8")])
+  [(set_attr "type" "load,load,load,fpload,fpload")
+   (set_attr "length" "4,4,8,4,8")
+   (set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
 
 ;; Variable V16QI/V8HI/V4SI extract from a register
 (define_insn_and_split "vsx_extract_<mode>_var"