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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Update ChangeLog.* Date: Fri, 21 Apr 2023 23:06:31 +0000 (GMT) [thread overview] Message-ID: <20230421230631.B8F543858D20@sourceware.org> (raw) https://gcc.gnu.org/g:3e3308ee2e7dcd770baeb1b6e336657ce73c88de commit 3e3308ee2e7dcd770baeb1b6e336657ce73c88de Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Apr 21 19:06:28 2023 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 58 +++--------------------------------------------- gcc/config/rs6000/vsx.md | 38 ++++++++++++++++++++++++------- 2 files changed, 33 insertions(+), 63 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 61634f875b1..c157e73db69 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,60 +1,8 @@ -==================== Branch work119, patch #52 ==================== +==================== Branch work119, patch #52 was reverted ==================== -Improve vec_extract of V4SF with variable element number. +==================== Branch work119, patch #51 was reverted ==================== -This patch adds a combine insn that merges loading up a vec_extract of V4SFmode -where the element number is variable combined with a conversion to DFmode. - -I also modified the insn for vec_extract of V4SFmode where the element number is -variable to split before register allocation. - -2023-04-21 Michael Meissner <meissner@linux.ibm.com> - -gcc/ - - * config/rs6000/vsx.md (vsx_extract_v4sf_var_load): Allow split before - register allocation. - (vsx_extract_v4sf_var_load_to_df): New insn. - -gcc/testsuite/ - - * gcc.target/powerpc/vec-extract-mem-float-2.c: New test. - -==================== Branch work119, patch #51 ==================== - -Combine vec_extract of V4SF with DF convert. - -This patch adds a combine insn that merges loading up a vec_extract of V4SFmode -where the element number is constant combined with a conversion to DFmode. - -In addition, I changed the vec_extract of V4SFmode where the element number is -constant without conversion to do the split before register allocation. I also -simplified the alternatives. - -2023-04-21 Michael Meissner <meissner@linux.ibm.com> - -gcc/ - - * config/rs6000/vsx.md (vsx_extract_v4sf_load): Allow split before - register allocation. - (vsx_extract_v4sf_to_df_load): New insn. - -gcc/testsuite/ - - * gcc.target/powerpc/vec-extract-mem-float-1.c: New test. - -==================== Branch work119, patch #50 ==================== - -Allow vec_extract support functions to be called before reload. - -2023-04-21 Michael Meissner <meissner@linux.ibm.com> - -gcc/ - - * config/rs6000/rs6000.cc (get_vector_offset): Allow being called before - register allocation. - (adjust_vec_address_pcrel): Likewise. - (rs6000_adjust_vec_address): Likewise. +==================== Branch work119, patch #50 was reverted ==================== ==================== Branch work119, patch #49 was reverted ==================== diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 417aff5e24b..17e56ab1ce4 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -3549,23 +3549,45 @@ [(set_attr "length" "8") (set_attr "type" "fp")]) +;; V4SF extract from memory convert to DFmode with constant element number. If +;; the element number is 0, we don't need a temporary register. (define_insn_and_split "*vsx_extract_v4sf_load" - [(set (match_operand:SF 0 "register_operand" "=f,v,v,?r") + [(set (match_operand:SF 0 "register_operand" "=wa,wa,?r,?r") (vec_select:SF - (match_operand:V4SF 1 "memory_operand" "m,Z,m,m") - (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n,n,n")]))) - (clobber (match_scratch:P 3 "=&b,&b,&b,&b"))] + (match_operand:V4SF 1 "memory_operand" "m,Q,m,Q") + (parallel + [(match_operand:QI 2 "const_0_to_3_operand" "O,n,O,n")]))) + (clobber (match_scratch:P 3 "=X,&b,X,&b"))] "VECTOR_MEM_VSX_P (V4SFmode)" "#" - "&& reload_completed" + "&& 1" [(set (match_dup 0) (match_dup 4))] { operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], operands[3], SFmode); } - [(set_attr "type" "fpload,fpload,fpload,load") - (set_attr "length" "8") - (set_attr "isa" "*,p7v,p9v,*")]) + [(set_attr "type" "fpload,fpload,load,load") + (set_attr "length" "4,8,4,8")]) + +;; V4SF extract from memory and convert to DFmode with constant element number. +(define_insn_and_split "*vsx_extract_v4sf_load_to_df" + [(set (match_operand:DF 0 "register_operand" "=wa,wa") + (float_extend:DF + (vec_select:SF + (match_operand:V4SF 1 "memory_operand" "m,Q") + (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n")])))) + (clobber (match_scratch:P 3 "=X,&b"))] + "VECTOR_MEM_VSX_P (V4SFmode)" + "#" + "&& 1" + [(set (match_dup 0) + (float_extend:DF (match_dup 4)))] +{ + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], + operands[3], SFmode); +} + [(set_attr "type" "fpload") + (set_attr "length" "4,8")]) ;; Variable V4SF extract from a register (define_insn_and_split "vsx_extract_v4sf_var"
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