[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:8ca5b658578bbfa9012f57884608b3bceb4124cd

commit 8ca5b658578bbfa9012f57884608b3bceb4124cd
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Apr 21 20:58:46 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 68 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 68 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 30b1619c5f2..0d54f525348 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,71 @@
+==================== Branch work119, patch #62 ====================
+
+Add vec_extract test cases.
+
+This patch adds test cases to verify that the vec_extract optimizations in
+include sign/zero extension with the load are generating code.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-char-1.c: New test.
+	* gcc.target/powerpc/vec-extract-mem-int-1.c: New test.
+	* gcc.target/powerpc/vec-extract-mem-short-1.c: New test.
+
+
+==================== Branch work119, patch #62 ====================
+
+Fold V16QI vsx_extract from memory with constant element with zero extension.
+
+This patch folds V16QI vsx_extract from memory where the element number is
+constant with zero extension to SImode/DImode.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v16qi_load_to_u<mode>): New insn.
+
+==================== Branch work119, patch #62 ====================
+
+Fold V8HI vsx_extract from memory with constant element with sign/zero extension.
+
+This patch folds V8HI vsx_extract from memory where the element number is
+constant with sign or zero extension to SImode/DImode.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v8hi_load_to_<su><mode>): New insn.
+
+==================== Branch work119, patch #62 ====================
+
+Fold V4SI sign or zero extension into vsx_extract from memory with constant element.
+
+This patch folds V4SI vsx_extract from memory where the element number is
+constant with sign or zero extension to DImode.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
+
+==================== Branch work119, patch #62 ====================
+
+Allow integer vec_extract to load vector registers.
+
+2023-04-21   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute
+	(vsx_extract_<mode>_load): Allow vec_extract of integer types with a
+	constant element number to load into vector registers.  Don't require a
+	base register temporary if the element number is 0.
+
 ==================== Branch work119, patch #61 ====================
 
 Combine vec_extract of V4SF with DF convert with variable element.