[gcc(refs/users/meissner/heads/work119)] Update ChangeLog.*

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:222af81c70a3c23cd31b453fdf524a52de07a2ff

commit 222af81c70a3c23cd31b453fdf524a52de07a2ff
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Apr 18 01:45:23 2023 -0400

    Update ChangeLog.*

Diff:
---
 gcc/ChangeLog.meissner | 75 ++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index 49592e20a32..88bdd55c470 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,5 +1,80 @@
 ==================== Branch work119, patch #21 ====================
 
+Add float/double conversions fro V4SI vec_extract
+
+This patch adds combiner insns to fold in conversion to float, double, or the
+IEEE 128-bit types (both signed and unsigned) of V4SI vec_extract with a
+constant element.  With this patch, GCC will load the SImode value directly into
+the vector register with LFIWZX or LFIWAX instead of doing a LWZ and then moving
+the value over with a direct move before the floating point conversion.
+
+2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (SIGN_ZERO): New code attribute.
+	(FL_CONSTRAINT): New code attribute.
+	(vsx_extract_v4si_load_to_<uns><mode): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
+
+==================== Branch work119, patch #21 ====================
+
+Add sign/zero conversions for V4SI vec_extract
+
+This patch adds combiner insns to fold in sign and zero extension of vec_extract
+of V4SI with a constant element when expanding to DImode.
+
+2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-int-2.c: New test.
+
+==================== Branch work119, patch #21 ====================
+
+Enhance vec_extract from int memory with constant element numbers.
+
+This patch adds a combine insn that merges loading up a vec_extract of V4SFmode
+where the element number is constant combined with a conversion to DFmode.
+Without this patch, the compiler would load the value into a GPR register and
+then do a direct move if it needs the value in a vector register.
+
+2023-04-18   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_to_df_load): New insn.
+
+gcc/testsuite/
+
+	* gcc.target/powerpc/vec-extract-mem-int-1.c: New test.
+
+==================== Branch work119, patch #22 ====================
+
+Fix typo in insn name.
+
+In doing other work, I noticed that there was an insn:
+
+	vsx_extract_v4sf_<mode>_load
+
+Which did not have an iterator.  I removed the useless <mode>.
+
+2023-04-17   Michael Meissner  <meissner@linux.ibm.com>
+
+gcc/
+
+	* config/rs6000/vsx.md (vsx_extract_v4sf_load): Rename from
+	vsx_extract_v4sf_<mode>_load.
+
+==================== Branch work119, patch #21 ====================
+
 Improve 64->128 bit zero extension on PowerPC
 
 2023-04-17   Michael Meissner  <meissner@linux.ibm.com>