public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-26 15:44 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-26 15:44 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b0fc20faa7fed4dd487ea359efba6963bd2fe300
commit b0fc20faa7fed4dd487ea359efba6963bd2fe300
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 11:43:21 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 67 ++++++++++++++++++++++
| 35 +++++++++++
| 35 +++++++++++
| 36 ++++++++++++
| 35 +++++++++++
| 36 ++++++++++++
6 files changed, 244 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0b7b26c2e2f..003bd534119 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,6 +4000,73 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "*,*,8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..61f021ee99f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e59ceae6866
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..052371e72ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..65ae21b1a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..6a2f23cfc57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-29 0:47 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-29 0:47 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:371e826e204a8063d66b8ee92d4fcbe4499f5366
commit 371e826e204a8063d66b8ee92d4fcbe4499f5366
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 20:47:17 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-28 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
| 35 +++++++++++++++++++++
| 35 +++++++++++++++++++++
| 36 ++++++++++++++++++++++
| 35 +++++++++++++++++++++
| 36 ++++++++++++++++++++++
5 files changed, 177 insertions(+)
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..61f021ee99f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e59ceae6866
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..052371e72ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..65ae21b1a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..6a2f23cfc57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-28 18:18 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-28 18:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1d27b30b506a528a4872e27956a22dc2d50418a7
commit 1d27b30b506a528a4872e27956a22dc2d50418a7
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 14:18:38 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-28 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 67 ++++++++++++++++++++++
| 35 +++++++++++
| 35 +++++++++++
| 36 ++++++++++++
| 35 +++++++++++
| 36 ++++++++++++
6 files changed, 244 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 4747aaa07e5..feb7fc753a6 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3998,6 +3998,73 @@
(set_attr "length" "8")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "non_altivec_memory_operand" "m,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "length" "8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "non_altivec_memory_operand" "m,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "non_altivec_memory_operand" "m")
+ (parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..61f021ee99f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e59ceae6866
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..052371e72ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..65ae21b1a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..6a2f23cfc57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-28 3:24 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-28 3:24 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:fd9da41171721803db850a784ae026643feeaef9
commit fd9da41171721803db850a784ae026643feeaef9
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 23:24:10 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 67 ++++++++++++++++++++++
| 35 +++++++++++
| 35 +++++++++++
| 36 ++++++++++++
| 35 +++++++++++
| 36 ++++++++++++
6 files changed, 244 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 18429a3c98a..6b1975df847 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3998,6 +3998,73 @@
(set_attr "length" "8")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "n,n")]))))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "length" "8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "n,n")]))))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "length" "8")
+ (set_attr "isa" "*,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m")
+ (parallel [(match_operand:QI 2 "const_int_operand" "n")]))))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..61f021ee99f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e59ceae6866
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..052371e72ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..65ae21b1a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..6a2f23cfc57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-25 15:54 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-25 15:54 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:ef21bf51066f5f9d041a63c3e50d418946686b41
commit ef21bf51066f5f9d041a63c3e50d418946686b41
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 11:53:47 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 67 ++++++++++++++++++++++
| 35 +++++++++++
| 35 +++++++++++
| 36 ++++++++++++
| 35 +++++++++++
| 36 ++++++++++++
6 files changed, 244 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0b7b26c2e2f..003bd534119 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,6 +4000,73 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "*,*,8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..046a203cebc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..6341a59433c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..f86935e51d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..e1cf0c91048
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..43e889acb5c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-25 6:29 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-25 6:29 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cb0f59ca59204c80c5a458c26b9ca23b3d26db43
commit cb0f59ca59204c80c5a458c26b9ca23b3d26db43
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 02:29:35 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 67 ++++++++++++++++++++++
| 35 +++++++++++
| 35 +++++++++++
| 36 ++++++++++++
| 35 +++++++++++
| 36 ++++++++++++
6 files changed, 244 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0b7b26c2e2f..003bd534119 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,6 +4000,73 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "*,*,8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..37cb9c0ae90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..3314f0cde3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..c8ba94ad824
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..f17bb874f01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..47c41027a28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-25 2:04 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-25 2:04 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:b6e92c004c25430c5a16c984b085f08971270f29
commit b6e92c004c25430c5a16c984b085f08971270f29
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 22:03:53 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 67 ++++++++++++++++++++++
| 35 +++++++++++
| 35 +++++++++++
| 63 ++++++++++++++++++++
| 35 +++++++++++
| 36 ++++++++++++
6 files changed, 271 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0b7b26c2e2f..003bd534119 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,6 +4000,73 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "*,*,8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..37cb9c0ae90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..3314f0cde3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..4d0e08908cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,63 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
+
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..f17bb874f01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..47c41027a28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-25 1:55 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-25 1:55 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:487a44be8605b917ff76a40f2ffdab94f5a52cde
commit 487a44be8605b917ff76a40f2ffdab94f5a52cde
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 21:55:29 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_z<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_z<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 67 ++++++++++++++++++++++
| 35 +++++++++++
| 35 +++++++++++
| 63 ++++++++++++++++++++
| 35 +++++++++++
| 36 ++++++++++++
6 files changed, 271 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 0b7b26c2e2f..a636a2a1470 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4000,6 +4000,73 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_z<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_z<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "*,*,8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..37cb9c0ae90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..3314f0cde3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..4d0e08908cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,63 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
+
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..f17bb874f01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..47c41027a28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended
@ 2023-04-25 1:48 Michael Meissner
0 siblings, 0 replies; 9+ messages in thread
From: Michael Meissner @ 2023-04-25 1:48 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:fb1a7b6917d4de9e45bafc64898f2697cd42dbea
commit fb1a7b6917d4de9e45bafc64898f2697cd42dbea
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 21:47:40 2023 -0400
Allow consant element vec_extract to be zero or sign extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be zero extended. It also allows vec_extract of V4SI
and V8HI vector types with constant element number to be sign extended.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_load_to_<su>d): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_z<GPR:mode>): New insn.
(vsx_extract_v8hi_load_to_z<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-char-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-int-2.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-1.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-2.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 67 ++++++++++++++++++++++
| 35 +++++++++++
| 35 +++++++++++
| 63 ++++++++++++++++++++
| 35 +++++++++++
| 36 ++++++++++++
6 files changed, 271 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b7759b77159..c9634980302 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -3999,6 +3999,73 @@
(set_attr "length" "*,*,8,*,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_z<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand" "m,o,Q,Z,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+(define_insn_and_split "*vsx_extract_v8hi_load_to_z<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "*,*,8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..37cb9c0ae90
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..3314f0cde3a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..4d0e08908cc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,63 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
+
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwa\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..f17bb874f01
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhz\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..47c41027a28
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlha\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhz\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-04-29 0:47 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-04-26 15:44 [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be zero or sign extended Michael Meissner
-- strict thread matches above, loose matches on Subject: below --
2023-04-29 0:47 Michael Meissner
2023-04-28 18:18 Michael Meissner
2023-04-28 3:24 Michael Meissner
2023-04-25 15:54 Michael Meissner
2023-04-25 6:29 Michael Meissner
2023-04-25 2:04 Michael Meissner
2023-04-25 1:55 Michael Meissner
2023-04-25 1:48 Michael Meissner
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).