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* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-26 15:46 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-26 15:46 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:474416a371f5120b769a45eb02772753733369f4
commit 474416a371f5120b769a45eb02772753733369f4
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 11:46:08 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 31 ++++++++++
| 19 +++++++
3 files changed, 116 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 497aac24319..4a93523090a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,6 +4107,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index e69de29bb2d..f6b027db3bc 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index e69de29bb2d..a1d3947fabb 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-29 3:40 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-29 3:40 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:32a7c2ff7d8ef24e262125ae233cd4ccbc5d9250
commit 32a7c2ff7d8ef24e262125ae233cd4ccbc5d9250
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 23:39:53 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 31 ++++++++++
| 19 +++++++
3 files changed, 116 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 59a3e83b7fa..8fc56bff892 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4179,6 +4179,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..f6b027db3bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
new file mode 100644
index 00000000000..a1d3947fabb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-28 18:36 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-28 18:36 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8a92aa10770cfc06fbf36e32f163df9967803030
commit 8a92aa10770cfc06fbf36e32f163df9967803030
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 14:36:17 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 31 ++++++++++
| 19 +++++++
3 files changed, 116 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 9d98b962f66..e33675781ce 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4108,6 +4108,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "non_altivec_memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "non_altivec_memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "non_altivec_memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index e69de29bb2d..f6b027db3bc 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index e69de29bb2d..a1d3947fabb 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-28 3:35 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-28 3:35 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8f8ce58d8d25dc027eca2382721a71f4bb54756d
commit 8f8ce58d8d25dc027eca2382721a71f4bb54756d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Apr 27 23:34:48 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-27 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 31 ++++++++++
| 19 +++++++
3 files changed, 116 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 2696d93becf..838caaab9ec 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4108,6 +4108,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index e69de29bb2d..f6b027db3bc 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index e69de29bb2d..a1d3947fabb 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-27 3:00 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-27 3:00 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:dc25a6c8bc782f6637c6c48416145f59d8d1e565
commit dc25a6c8bc782f6637c6c48416145f59d8d1e565
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 22:59:47 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 31 ++++++++++
| 19 +++++++
3 files changed, 116 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 19a502b99a3..c21571a03cf 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4110,6 +4110,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index e69de29bb2d..f6b027db3bc 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index e69de29bb2d..a1d3947fabb 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-27 2:58 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-27 2:58 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a18459b28378eacf5e1c73d5f88d942b34b7cbef
commit a18459b28378eacf5e1c73d5f88d942b34b7cbef
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Apr 26 22:57:59 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-26 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 31 ++++++++++
| 19 +++++++
3 files changed, 116 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 19a502b99a3..62f9702554a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4110,6 +4110,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
index e69de29bb2d..f6b027db3bc 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
index e69de29bb2d..a1d3947fabb 100644
--- a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-25 15:56 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-25 15:56 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:8dc03f9e5da620cc41dec0f22280473b1ac2a4a3
commit 8dc03f9e5da620cc41dec0f22280473b1ac2a4a3
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 11:55:51 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-25 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 31 ++++++++++
| 19 +++++++
3 files changed, 116 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 497aac24319..4a93523090a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,6 +4107,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..f6b027db3bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
new file mode 100644
index 00000000000..a1d3947fabb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-25 6:41 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-25 6:41 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:1744cea5053f9c3674165335d35f862ef3a2763d
commit 1744cea5053f9c3674165335d35f862ef3a2763d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 02:40:55 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 31 ++++++++++
| 19 +++++++
3 files changed, 116 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 497aac24319..4a93523090a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,6 +4107,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..f6b027db3bc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,31 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. Both uses
+ generate a rldicl to clear the bits in the variable element number, but this
+ test verifies that there is no rldicl after the lwzx to do the zero
+ extension. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v4si_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v4si_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no extra rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mlwzx\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mrldicl\M} 2 } } */
+/* { dg-final { scan-assembler-times {\msldi\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
new file mode 100644
index 00000000000..a1d3947fabb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-25 6:39 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-25 6:39 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:a4af2c4c975dfe7e73ccaa1f942f80f404f6ec2f
commit a4af2c4c975dfe7e73ccaa1f942f80f404f6ec2f
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Tue Apr 25 02:39:03 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 66 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 497aac24319..4a93523090a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,6 +4107,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
^ permalink raw reply [flat|nested] 10+ messages in thread
* [gcc(refs/users/meissner/heads/work119)] Allow variable element vec_extract to be sign or zero extended
@ 2023-04-25 2:51 Michael Meissner
0 siblings, 0 replies; 10+ messages in thread
From: Michael Meissner @ 2023-04-25 2:51 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:69f67cf89c8586efaab1e15aa78c4b983e702715
commit 69f67cf89c8586efaab1e15aa78c4b983e702715
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Mon Apr 24 22:51:15 2023 -0400
Allow variable element vec_extract to be sign or zero extended
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
variable element number to be loaded with sign or zero extension, and GCC will
not generate a separate zero/sign extension instruction.
2023-04-24 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (vsx_extract_v4si_var_load_to_<su>di): New insn.
(vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>): New insn.
(vsx_extract_v8hi_var_load_to_s<mode>): New insn.
gcc/testsuite/
* gcc.target/powerpc/vec-extract-mem-int-3.c: New file.
* gcc.target/powerpc/vec-extract-mem-short-3.c: New file.
Diff:
---
gcc/config/rs6000/vsx.md | 66 ++++++++++++++++++++++
| 27 +++++++++
| 19 +++++++
3 files changed, 112 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 497aac24319..4a93523090a 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4107,6 +4107,72 @@
[(set_attr "type" "load,fpload")
(set_attr "isa" "*,<VSX_EX_ISA>")])
+;; Variable V4SI extract from memory with sign or zero conversion to DImode.
+(define_insn_and_split "*vsx_extract_v4si_var_load_to_<su>di"
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,wa")
+ (any_extend:DI
+ (unspec:SI
+ [(match_operand:V4SI 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,fpload")])
+
+;; Variable V8HI/V16QI extract from memory with zero conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_var_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,v")
+ (zero_extend:GPR
+ (unspec:<VSX_EXTRACT_I2:MODE>
+ [(match_operand:VSX_EXTRACT_I2 1 "memory_operand" "Q,Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r,r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:MODE>mode);
+}
+ [(set_attr "type" "load,fpload")
+ (set_attr "isa" "*,p9v")])
+
+;; Variable V8HI extract from memory with sign conversion to either
+;; SImode or DImode.
+(define_insn_and_split "*vsx_extract_v8hi_var_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
+ (sign_extend:GPR
+ (unspec:HI
+ [(match_operand:V8HI 1 "memory_operand" "Q")
+ (match_operand:DI 2 "gpc_reg_operand" "r")]
+ UNSPEC_VSX_EXTRACT)))
+ (clobber (match_scratch:DI 3 "=&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& 1"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")])
+
;; ISA 3.1 extract
(define_expand "vextractl<mode>"
[(set (match_operand:V2DI 0 "altivec_register_operand")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
new file mode 100644
index 00000000000..dca53f3fe3d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-3.c
@@ -0,0 +1,27 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ SImode and fold both zero and sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+unsigned long long
+extract_uns_v8hi_var (vector unsigned int *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwzx, no rldicl. */
+}
+
+/* { dg-final { scan-assembler {\mlwax\M} } } */
+/* { dg-final { scan-assembler {\mlwzx\M} } } */
+/* { dg-final { scan-assembler-not {\mlw[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
new file mode 100644
index 00000000000..a1d3947fabb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-3.c
@@ -0,0 +1,19 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-options "-O2 -mvsx" } */
+/* { dg-require-effective-target powerpc_vsx_ok } */
+
+/* Test to verify that the vec_extract with variable element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+#include <stddef.h>
+
+long long
+extract_sign_v8hi_var (vector short *p, size_t n)
+{
+ return vec_extract (*p, n); /* lwax, no extsw. */
+}
+
+/* { dg-final { scan-assembler {\mlhax\M} } } */
+/* { dg-final { scan-assembler-not {\mlh[az]\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
^ permalink raw reply [flat|nested] 10+ messages in thread
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