public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be loaded into vector registers.
Date: Fri, 28 Apr 2023 22:56:00 +0000 (GMT) [thread overview]
Message-ID: <20230428225600.8CD633858D37@sourceware.org> (raw)
https://gcc.gnu.org/g:1941eb946d423b0ffffb66eef1d94377a559d94c
commit 1941eb946d423b0ffffb66eef1d94377a559d94c
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Apr 28 18:55:39 2023 -0400
Allow consant element vec_extract to be loaded into vector registers.
This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a
constant element number to be loaded into vector registers directly.
This patch also adds support for optimzing 0 element number to not need a base
register tempoary. Likewise, if we have an offsettable address, we don't need
to allocate a scratch register.
2023-04-28 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute.
(vsx_extract_<mode>_load): Allow vector registers to be loaded. Add
optimizations for loading up element 0 and/or with an offsettable
address.
Diff:
---
gcc/config/rs6000/vsx.md | 84 ++++++++++++++++++++++
| 35 +++++++++
| 35 +++++++++
| 36 ++++++++++
| 35 +++++++++
| 36 ++++++++++
6 files changed, 261 insertions(+)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 73b1e8896fd..f25b29855f4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -4023,6 +4023,90 @@
(set_attr "length" "4,4,8,4,8")
(set_attr "isa" "*,*,*,<VSX_EX_ISA>,<VSX_EX_ISA>")])
+;; Fold extracting a V4SI element with a constant element with either sign or
+;; zero extension to DImode.
+;; Alternatives:
+;; 1: GPR, element 0, normal address, no modification
+;; 2: GPR, element 0-3, offsettable address
+;; 3: GPR, element 0-3, single register (offset to op[3])
+;; 4: VSX, element 0, X-form address, no modification
+;; 5: VSX, element 0-3, single register (offset to op[3])
+(define_insn_and_split "*vsx_extract_v4si_load_to_<su>di"
+ [(set (match_operand:DI 0 "register_operand" "=r,r,r,wa,wa")
+ (any_extend:DI
+ (vec_select:SI
+ (match_operand:V4SI 1 "memory_operand" "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_0_to_3_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (V4SImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (any_extend:DI (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ SImode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")])
+
+;; Fold extracting a V8HI/V4SI element with a constant element with zero
+;; extension to either DImode or SImode.
+;; Alternatives:
+;; 1: GPR, element 0, normal address, no modification
+;; 2: GPR, element 0-3, offsettable address
+;; 3: GPR, element 0-3, single register (offset to op[3])
+;; 4: VMX, element 0, X-form address, no modification
+;; 5: VMX, element 0-3, single register (offset to op[3])
+(define_insn_and_split "*vsx_extract_<VSX_EXTRACT_I2:mode>_load_to_u<GPR:mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r,v,v")
+ (zero_extend:GPR
+ (vec_select:<VEC_base>
+ (match_operand:VSX_EXTRACT_I2 1 "memory_operand"
+ "m,o,m,Z,Q")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n,O,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b,X,&b"))]
+ "VECTOR_MEM_VSX_P (<VSX_EXTRACT_I2:MODE>mode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (zero_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ <VSX_EXTRACT_I2:VEC_base>mode);
+}
+ [(set_attr "type" "load,load,load,fpload,fpload")
+ (set_attr "length" "*,*,8,*,8")
+ (set_attr "isa" "*,*,*,p9v,p9v")])
+
+;; Fold extracting a V8HI element with a constant element with sign extension
+;; to either DImode or SImode.
+;; Alternatives:
+;; 1: GPR, element 0, normal address, no modification
+;; 2: GPR, element 0-3, offsettable address
+;; 3: GPR, element 0-3, single register (offset to op[3])
+(define_insn_and_split "*vsx_extract_v8hi_load_to_s<mode>"
+ [(set (match_operand:GPR 0 "register_operand" "=r,r,r")
+ (sign_extend:GPR
+ (vec_select:HI
+ (match_operand:V8HI 1 "memory_operand" "m,o,m")
+ (parallel [(match_operand:QI 2 "const_int_operand" "O,n,n")]))))
+ (clobber (match_scratch:DI 3 "=X,X,&b"))]
+ "VECTOR_MEM_VSX_P (V8HImode) && TARGET_DIRECT_MOVE_64BIT"
+ "#"
+ "&& reload_completed"
+ [(set (match_dup 0)
+ (sign_extend:GPR (match_dup 4)))]
+{
+ operands[4] = rs6000_adjust_vec_address (operands[0], operands[1],
+ operands[2], operands[3],
+ HImode);
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "8")])
+
;; Variable V16QI/V8HI/V4SI extract from a register
(define_insn_and_split "vsx_extract_<mode>_var"
[(set (match_operand:<VEC_base> 0 "gpc_reg_operand" "=r,r")
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
new file mode 100644
index 00000000000..61f021ee99f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-char-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ QImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v16qi_element_0 (vector unsigned char *p)
+{
+ return vec_extract (*p, 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_1 (vector unsigned char *p)
+{
+ return vec_extract (*p, 1); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_0_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v16qi_element_3_index_4 (vector unsigned char *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlbzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
new file mode 100644
index 00000000000..e59ceae6866
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v4si_0 (vector unsigned int *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_1 (vector unsigned int *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_0_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 0); /* lwz, no rldicl. */
+}
+
+unsigned long long
+extract_uns_v4si_element_3_index_4 (vector unsigned int *p)
+{
+ return vec_extract (p[4], 3); /* lwz, no rldicl. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrldicl\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
new file mode 100644
index 00000000000..052371e72ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-int-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v4si_0 (vector int *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_1 (vector int *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_0_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v4si_element_3_index_4 (vector int *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlwax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlwzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsw\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
new file mode 100644
index 00000000000..65ae21b1a1c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-1.c
@@ -0,0 +1,35 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ SImode and fold zero extension into the load. */
+
+#include <altivec.h>
+
+unsigned long long
+extract_uns_v8hi_0 (vector unsigned short *p)
+{
+ return vec_extract (*p, 0); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_1 (vector unsigned short *p)
+{
+ return vec_extract (*p, 1); /* lwz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_0_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 0); /* lbz, no rlwinm. */
+}
+
+unsigned long long
+extract_uns_v8hi_element_3_index_4 (vector unsigned short *p)
+{
+ return vec_extract (p[4], 3); /* lbz, no rlwinm. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhzx?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mrlwinm\M} } } */
--git a/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
new file mode 100644
index 00000000000..6a2f23cfc57
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-extract-mem-short-2.c
@@ -0,0 +1,36 @@
+/* { dg-do compile { target lp64 } } */
+/* { dg-require-effective-target powerpc_p8vector_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Test to verify that the vec_extract with constant element numbers can load
+ HImode and fold sign extension into the load. */
+
+#include <altivec.h>
+
+long long
+extract_sign_v8hi_0 (vector short *p)
+{
+ return vec_extract (*p, 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_1 (vector short *p)
+{
+ return vec_extract (*p, 1); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_0_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 0); /* lwa, no extsw. */
+}
+
+long long
+extract_sign_v8hi_element_3_index_4 (vector short *p)
+{
+ return vec_extract (p[4], 3); /* lwa, no extsw. */
+}
+
+/* { dg-final { scan-assembler-times {\mlhax?\M} 4 } } */
+/* { dg-final { scan-assembler-not {\mlhzx?\M} } } */
+/* { dg-final { scan-assembler-not {\mextsh\M} } } */
next reply other threads:[~2023-04-28 22:56 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-28 22:56 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2023-04-29 3:11 Michael Meissner
2023-04-28 22:36 Michael Meissner
2023-04-28 18:13 Michael Meissner
2023-04-28 18:08 Michael Meissner
2023-04-27 22:03 Michael Meissner
2023-04-25 1:54 Michael Meissner
2023-04-24 23:20 Michael Meissner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230428225600.8CD633858D37@sourceware.org \
--to=meissner@gcc.gnu.org \
--cc=gcc-cvs@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).