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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work119)] Allow consant element vec_extract to be loaded into vector registers. Date: Sat, 29 Apr 2023 03:11:42 +0000 (GMT) [thread overview] Message-ID: <20230429031142.D24553858D37@sourceware.org> (raw) https://gcc.gnu.org/g:404f0dd14879585ae9625c3714d7f58190074af3 commit 404f0dd14879585ae9625c3714d7f58190074af3 Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Apr 28 23:11:24 2023 -0400 Allow consant element vec_extract to be loaded into vector registers. This patch allows vec_extract of V4SI, V8HI, and V16QI vector types with a constant element number to be loaded into vector registers directly. This patch also adds support for optimzing 0 element number to not need a base register tempoary. Likewise, if we have an offsettable address, we don't need to allocate a scratch register. 2023-04-28 Michael Meissner <meissner@linux.ibm.com> gcc/ * config/rs6000/vsx.md (VSX_EX_ISA): New mode attribute. (vsx_extract_<mode>_load): Allow vector registers to be loaded. Add optimizations for loading up element 0 and/or with an offsettable address. Diff: --- gcc/config/rs6000/vsx.md | 38 +++++++++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f42793fe012..0118d4788cb 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -223,6 +223,12 @@ (V8HI "v") (V4SI "wa")]) +;; Mode attribute to give the isa constraint for accessing Altivec registers +;; with vector extract and insert operations. +(define_mode_attr VSX_EX_ISA [(V16QI "p9v") + (V8HI "p9v") + (V4SI "p8v")]) + ;; Mode iterator for binary floating types other than double to ;; optimize convert to that floating point type from an extract ;; of an integer type @@ -4008,23 +4014,37 @@ } [(set_attr "type" "mfvsr")]) -;; Optimize extracting a single scalar element from memory. +;; Extract a V16QI/V8HI/V4SI element from memory with a constant element +;; number. For vector registers, we require X-form addressing. +;; Alternatives: +;; Reg: Ele: Cpu: Addr: need scratch +;; 1: GPR 0 any normal address no +;; 2: GPR 1-3 any offsettable address no +;; 3: GPR 1-3 any single register yes +;; 4: wa/v 0 p8/p9 reg+reg or reg no +;; 5: wa/v 1-3 p8/p9 single register yes (define_insn_and_split "*vsx_extract_<mode>_load" - [(set (match_operand:<VEC_base> 0 "register_operand" "=r") + [(set (match_operand:<VEC_base> 0 "register_operand" + "=r, r, r, <VSX_EX>, <VSX_EX>") (vec_select:<VEC_base> - (match_operand:VSX_EXTRACT_I 1 "memory_operand" "m") - (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" "n")]))) - (clobber (match_scratch:DI 3 "=&b"))] + (match_operand:VSX_EXTRACT_I 1 "memory_operand" + "m, o, m, Z, Q") + (parallel [(match_operand:QI 2 "<VSX_EXTRACT_PREDICATE>" + "O, n, n, O, n")]))) + (clobber (match_scratch:DI 3 + "=X, X, &b, X, &b"))] "VECTOR_MEM_VSX_P (<MODE>mode) && TARGET_DIRECT_MOVE_64BIT" "#" "&& reload_completed" [(set (match_dup 0) (match_dup 4))] { - operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], operands[2], - operands[3], <VEC_base>mode); + operands[4] = rs6000_adjust_vec_address (operands[0], operands[1], + operands[2], operands[3], + <VEC_base>mode); } - [(set_attr "type" "load") - (set_attr "length" "8")]) + [(set_attr "type" "load, load, load, fpload, fpload") + (set_attr "length" "*, *, 8, *, 8") + (set_attr "isa" "*, *, *, <VSX_EX_ISA>, <VSX_EX_ISA>")]) ;; Variable V16QI/V8HI/V4SI extract from a register (define_insn_and_split "vsx_extract_<mode>_var"
next reply other threads:[~2023-04-29 3:11 UTC|newest] Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top 2023-04-29 3:11 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2023-04-28 22:56 Michael Meissner 2023-04-28 22:36 Michael Meissner 2023-04-28 18:13 Michael Meissner 2023-04-28 18:08 Michael Meissner 2023-04-27 22:03 Michael Meissner 2023-04-25 1:54 Michael Meissner 2023-04-24 23:20 Michael Meissner
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