* [PATCH] lround for PowerPC
@ 2015-11-22 3:21 David Edelsohn
2015-11-22 8:51 ` Richard Biener
0 siblings, 1 reply; 11+ messages in thread
From: David Edelsohn @ 2015-11-22 3:21 UTC (permalink / raw)
To: Segher Boessenkool, William J. Schmidt; +Cc: GCC Patches
PowerPC was missing a definition of the lroundMN pattern, which can be
implemented with VSX instructions available in Power7. Below is a
first draft.
- David
* config/rs6000/rs6000.md (*xsrdpidf2): New define_insn.
(lrounddfdi2): New define_expand.
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 8c53c40..eadbe1d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -77,6 +77,7 @@
UNSPEC_FRIN
UNSPEC_FRIP
UNSPEC_FRIZ
+ UNSPEC_XSRDPI
UNSPEC_LD_MPIC ; load_macho_picbase
UNSPEC_RELD_MPIC ; re-load_macho_picbase
UNSPEC_MPIC_CORRECT ; macho_correct_pic
@@ -5245,6 +5246,27 @@
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_<Fs>")])
+(define_insn "*xsrdpidf2"
+ [(set (match_operand:DF 0 "gpc_reg_operand" "=<Fv>")
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "<Fv>")]
+ UNSPEC_XSRDPI))]
+ "TARGET_DF_FPR && TARGET_POPCNTD"
+ "xsrdpi %0,%1"
+ [(set_attr "type" "fp")])
+
+(define_expand "lrounddfdi2"
+ [(set (match_dup 2)
+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "<Fv>")]
+ UNSPEC_XSRDPI))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=d")
+ (unspec:DI [(match_dup 2)]
+ UNSPEC_FCTID))]
+ "TARGET_DF_FPR && TARGET_POPCNTD
+ && flag_unsafe_math_optimizations && !flag_trapping_math"
+{
+ operands[2] = gen_reg_rtx (DFmode);
+})
+
; An UNSPEC is used so we don't have to support SImode in FP registers.
(define_insn "stfiwx"
[(set (match_operand:SI 0 "memory_operand" "=Z")
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-22 3:21 [PATCH] lround for PowerPC David Edelsohn
@ 2015-11-22 8:51 ` Richard Biener
2015-11-22 14:39 ` David Edelsohn
2015-11-22 20:58 ` David Edelsohn
0 siblings, 2 replies; 11+ messages in thread
From: Richard Biener @ 2015-11-22 8:51 UTC (permalink / raw)
To: David Edelsohn, Segher Boessenkool, William J. Schmidt; +Cc: GCC Patches
On November 22, 2015 2:52:53 AM GMT+01:00, David Edelsohn <dje.gcc@gmail.com> wrote:
>PowerPC was missing a definition of the lroundMN pattern, which can be
>implemented with VSX instructions available in Power7. Below is a
>first draft.
>
>- David
>
>* config/rs6000/rs6000.md (*xsrdpidf2): New define_insn.
>(lrounddfdi2): New define_expand.
>
>diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
>index 8c53c40..eadbe1d 100644
>--- a/gcc/config/rs6000/rs6000.md
>+++ b/gcc/config/rs6000/rs6000.md
>@@ -77,6 +77,7 @@
> UNSPEC_FRIN
> UNSPEC_FRIP
> UNSPEC_FRIZ
>+ UNSPEC_XSRDPI
> UNSPEC_LD_MPIC ; load_macho_picbase
> UNSPEC_RELD_MPIC ; re-load_macho_picbase
> UNSPEC_MPIC_CORRECT ; macho_correct_pic
>@@ -5245,6 +5246,27 @@
> [(set_attr "type" "fp")
> (set_attr "fp_type" "fp_addsub_<Fs>")])
>
>+(define_insn "*xsrdpidf2"
>+ [(set (match_operand:DF 0 "gpc_reg_operand" "=<Fv>")
>+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "<Fv>")]
>+ UNSPEC_XSRDPI))]
>+ "TARGET_DF_FPR && TARGET_POPCNTD"
>+ "xsrdpi %0,%1"
>+ [(set_attr "type" "fp")])
>+
>+(define_expand "lrounddfdi2"
>+ [(set (match_dup 2)
>+ (unspec:DF [(match_operand:DF 1 "gpc_reg_operand" "<Fv>")]
>+ UNSPEC_XSRDPI))
>+ (set (match_operand:DI 0 "gpc_reg_operand" "=d")
>+ (unspec:DI [(match_dup 2)]
>+ UNSPEC_FCTID))]
>+ "TARGET_DF_FPR && TARGET_POPCNTD
>+ && flag_unsafe_math_optimizations && !flag_trapping_math"
Why unsafe-math?
Richard.
>+{
>+ operands[2] = gen_reg_rtx (DFmode);
>+})
>+
>; An UNSPEC is used so we don't have to support SImode in FP registers.
> (define_insn "stfiwx"
> [(set (match_operand:SI 0 "memory_operand" "=Z")
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-22 8:51 ` Richard Biener
@ 2015-11-22 14:39 ` David Edelsohn
2015-11-22 20:58 ` David Edelsohn
1 sibling, 0 replies; 11+ messages in thread
From: David Edelsohn @ 2015-11-22 14:39 UTC (permalink / raw)
To: Richard Biener; +Cc: Segher Boessenkool, William J. Schmidt, GCC Patches
On Sun, Nov 22, 2015 at 2:34 AM, Richard Biener
<richard.guenther@gmail.com> wrote:
> On November 22, 2015 2:52:53 AM GMT+01:00, David Edelsohn <dje.gcc@gmail.com> wrote:
>>PowerPC was missing a definition of the lroundMN pattern, which can be
>>implemented with VSX instructions available in Power7. Below is a
>>first draft.
> Why unsafe-math?
It's a first draft. I want to re-confirm that the combined
instructions set all of the correct flags.
The patterns should work in SF and DF modes, but currently trigger a
reload failure in SFmode.
Thanks, David
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-22 8:51 ` Richard Biener
2015-11-22 14:39 ` David Edelsohn
@ 2015-11-22 20:58 ` David Edelsohn
2015-11-23 22:15 ` Michael Meissner
1 sibling, 1 reply; 11+ messages in thread
From: David Edelsohn @ 2015-11-22 20:58 UTC (permalink / raw)
To: Richard Biener, Segher Boessenkool; +Cc: William J. Schmidt, GCC Patches
v2 of the patch. Seems to pass the GCC testsuite, although the
testsuite doesn't stress FP.
There is something wrong with current VSX SFmode constraints.
Index: rs6000.md
===================================================================
--- rs6000.md (revision 230723)
+++ rs6000.md (working copy)
@@ -77,6 +77,7 @@
UNSPEC_FRIN
UNSPEC_FRIP
UNSPEC_FRIZ
+ UNSPEC_XSRDPI
UNSPEC_LD_MPIC ; load_macho_picbase
UNSPEC_RELD_MPIC ; re-load_macho_picbase
UNSPEC_MPIC_CORRECT ; macho_correct_pic
@@ -5500,6 +5501,27 @@
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_<Fs>")])
+(define_insn "*xsrdpi<mode>2"
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=wa")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")]
+ UNSPEC_XSRDPI))]
+ "TARGET_<MODE>_FPR && TARGET_POPCNTD"
+ "xsrdpi %x0,%x1"
+ [(set_attr "type" "fp")
+ (set_attr "fp_type" "fp_addsub_<Fs>")])
+
+(define_expand "lround<mode>di2"
+ [(set (match_dup 2)
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")]
+ UNSPEC_XSRDPI))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=d")
+ (unspec:DI [(match_dup 2)]
+ UNSPEC_FCTID))]
+ "TARGET_<MODE>_FPR && TARGET_POPCNTD"
+{
+ operands[2] = gen_reg_rtx (<MODE>mode);
+})
+
; An UNSPEC is used so we don't have to support SImode in FP registers.
(define_insn "stfiwx"
[(set (match_operand:SI 0 "memory_operand" "=Z")
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-22 20:58 ` David Edelsohn
@ 2015-11-23 22:15 ` Michael Meissner
2015-11-24 0:06 ` David Edelsohn
2015-11-24 0:16 ` Michael Meissner
0 siblings, 2 replies; 11+ messages in thread
From: Michael Meissner @ 2015-11-23 22:15 UTC (permalink / raw)
To: David Edelsohn
Cc: Richard Biener, Segher Boessenkool, William J. Schmidt, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 1543 bytes --]
David ping'ed me on internal IRC, and I had a thinko in terms of the use of the
<Fv> mode attribute. In some of the uses (such as abs, smax, etc.) we want to
use ISA 2.06 instructions on SFmode, while in other uses (add, mul, etc.) we
want to use it only if we have the ISA 2.07 instrucitons.
I have split these mode attributes into Fv and Fv2 and gone through all of the
uses in the compiler to use the appropriate attribute. I have built a cross
compiler on x86, but it blew up on a big endian power7 with a segmentation
violation that I need to look into. I'm also building on a little endian
power8 right now, and it has gotten further.
2015-11-23 David Edelsohn <dje.gcc@gmail.com>
Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec.
(Fv2): New mode attribute to be used when ISA 2.06 instructions
are used on SF/DF values.
(abs<mode>2_fpr): Use <Fv2> instead of <Fv>.
(nabs<mode>2_fpr): Likewise.
(neg<mode>2_fpr): Likewise.
(copysign<mode>3_fcpsgn): Likewise.
(smax<mode>3_vsx): Likewise.
(smin<mode>3_vsx): Likewise.
(floatsi<mode>2_lfiwax): Likewise.
(floatunssi<mode>2_lfiwz): Likewise.
(fctiwz_<mode>): Likewise.
(fctiwuz_<mode>): Likewise.
(btrunc<mode>2): Likewise.
(ceil<mode>2): Likewise.
(floor<mode>2): Likewise.
(xsrdpi<mode>): Add support for the lround function.
(lround<mode>2): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: lround.patch02b --]
[-- Type: text/plain, Size: 8429 bytes --]
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 230768)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -77,6 +77,7 @@ (define_c_enum "unspec"
UNSPEC_FRIN
UNSPEC_FRIP
UNSPEC_FRIZ
+ UNSPEC_XSRDPI
UNSPEC_LD_MPIC ; load_macho_picbase
UNSPEC_RELD_MPIC ; re-load_macho_picbase
UNSPEC_MPIC_CORRECT ; macho_correct_pic
@@ -491,9 +492,17 @@ (define_mode_attr Fvsx [(SF "sp") (DF "
; SF/DF constraint for arithmetic on traditional floating point registers
(define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
-; SF/DF constraint for arithmetic on VSX registers
+; SF/DF constraint for arithmetic on VSX registers. This is intended to be
+; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
+; instructions added in ISA 2.07 (power8)
(define_mode_attr Fv [(SF "wy") (DF "ws") (DI "wi")])
+; SF/DF constraint for arithmetic on VSX registers using instructions added in
+; ISA 2.06 (power7). This includes instructions that normally target DF mode,
+; but are used on SFmode, since internally SFmode values are kept in the DFmode
+; format.
+(define_mode_attr Fv2 [(SF "ww") (DF "ws") (DI "wi")])
+
; SF/DF constraint for arithmetic on altivec registers
(define_mode_attr Fa [(SF "wu") (DF "wv")])
@@ -4299,8 +4308,8 @@ (define_expand "abs<mode>2"
"")
(define_insn "*abs<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fabs %0,%1
@@ -4309,10 +4318,10 @@ (define_insn "*abs<mode>2_fpr"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "*nabs<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
(neg:SFDF
(abs:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>"))))]
"TARGET_<MODE>_FPR"
"@
fnabs %0,%1
@@ -4327,8 +4336,8 @@ (define_expand "neg<mode>2"
"")
(define_insn "*neg<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fneg %0,%1
@@ -4557,9 +4566,9 @@ (define_expand "copysign<mode>3"
;; Use an unspec rather providing an if-then-else in RTL, to prevent the
;; compiler from optimizing -0.0
(define_insn "copysign<mode>3_fcpsgn"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_COPYSIGN))]
"TARGET_<MODE>_FPR && TARGET_CMPB"
"@
@@ -4593,9 +4602,9 @@ (define_expand "smax<mode>3"
})
(define_insn "*smax<mode>3_vsx"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR && TARGET_VSX"
"xsmaxdp %x0,%x1,%x2"
[(set_attr "type" "fp")])
@@ -4613,9 +4622,9 @@ (define_expand "smin<mode>3"
})
(define_insn "*smin<mode>3_vsx"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR && TARGET_VSX"
"xsmindp %x0,%x1,%x2"
[(set_attr "type" "fp")])
@@ -4836,7 +4845,7 @@ (define_insn "lfiwax"
; not be needed and also in case the insns are deleted as dead code.
(define_insn_and_split "floatsi<mode>2_lfiwax"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv2>")
(float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wj"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
@@ -4911,7 +4920,7 @@ (define_insn "lfiwzx"
[(set_attr "type" "fpload,fpload,mftgpr")])
(define_insn_and_split "floatunssi<mode>2_lfiwzx"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv2>")
(unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wj"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
@@ -5346,7 +5355,7 @@ (define_insn "*fixuns_trunc<mode>di2_fct
; before the instruction.
(define_insn "fctiwz_<mode>"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
- (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
+ (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>"))]
UNSPEC_FCTIWZ))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"@
@@ -5357,7 +5366,7 @@ (define_insn "fctiwz_<mode>"
(define_insn "fctiwuz_<mode>"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(unspec:DI [(unsigned_fix:SI
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>"))]
UNSPEC_FCTIWUZ))]
"TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
"@
@@ -5458,8 +5467,8 @@ (define_insn "lrint<mode>di2"
[(set_attr "type" "fp")])
(define_insn "btrunc<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_FRIZ))]
"TARGET_<MODE>_FPR && TARGET_FPRND"
"@
@@ -5469,8 +5478,8 @@ (define_insn "btrunc<mode>2"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "ceil<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_FRIP))]
"TARGET_<MODE>_FPR && TARGET_FPRND"
"@
@@ -5480,8 +5489,8 @@ (define_insn "ceil<mode>2"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "floor<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_FRIM))]
"TARGET_<MODE>_FPR && TARGET_FPRND"
"@
@@ -5500,6 +5509,27 @@ (define_insn "round<mode>2"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_<Fs>")])
+(define_insn "*xsrdpi<mode>2"
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Fv2>")]
+ UNSPEC_XSRDPI))]
+ "TARGET_<MODE>_FPR && TARGET_VSX"
+ "xsrdpi %x0,%x1"
+ [(set_attr "type" "fp")
+ (set_attr "fp_type" "fp_addsub_<Fs>")])
+
+(define_expand "lround<mode>di2"
+ [(set (match_dup 2)
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")]
+ UNSPEC_XSRDPI))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=d")
+ (unspec:DI [(match_dup 2)]
+ UNSPEC_FCTID))]
+ "TARGET_<MODE>_FPR && TARGET_VSX"
+{
+ operands[2] = gen_reg_rtx (<MODE>mode);
+})
+
; An UNSPEC is used so we don't have to support SImode in FP registers.
(define_insn "stfiwx"
[(set (match_operand:SI 0 "memory_operand" "=Z")
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-23 22:15 ` Michael Meissner
@ 2015-11-24 0:06 ` David Edelsohn
2015-11-24 18:51 ` Michael Meissner
2015-11-24 23:01 ` Michael Meissner
2015-11-24 0:16 ` Michael Meissner
1 sibling, 2 replies; 11+ messages in thread
From: David Edelsohn @ 2015-11-24 0:06 UTC (permalink / raw)
To: Michael Meissner, Richard Biener, Segher Boessenkool,
William J. Schmidt, GCC Patches
On Mon, Nov 23, 2015 at 4:56 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> David ping'ed me on internal IRC, and I had a thinko in terms of the use of the
> <Fv> mode attribute. In some of the uses (such as abs, smax, etc.) we want to
> use ISA 2.06 instructions on SFmode, while in other uses (add, mul, etc.) we
> want to use it only if we have the ISA 2.07 instrucitons.
>
> I have split these mode attributes into Fv and Fv2 and gone through all of the
> uses in the compiler to use the appropriate attribute. I have built a cross
> compiler on x86, but it blew up on a big endian power7 with a segmentation
> violation that I need to look into. I'm also building on a little endian
> power8 right now, and it has gotten further.
>
> 2015-11-23 David Edelsohn <dje.gcc@gmail.com>
> Michael Meissner <meissner@linux.vnet.ibm.com>
>
> * config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec.
> (Fv2): New mode attribute to be used when ISA 2.06 instructions
> are used on SF/DF values.
> (abs<mode>2_fpr): Use <Fv2> instead of <Fv>.
> (nabs<mode>2_fpr): Likewise.
> (neg<mode>2_fpr): Likewise.
> (copysign<mode>3_fcpsgn): Likewise.
> (smax<mode>3_vsx): Likewise.
> (smin<mode>3_vsx): Likewise.
> (floatsi<mode>2_lfiwax): Likewise.
> (floatunssi<mode>2_lfiwz): Likewise.
> (fctiwz_<mode>): Likewise.
> (fctiwuz_<mode>): Likewise.
> (btrunc<mode>2): Likewise.
> (ceil<mode>2): Likewise.
> (floor<mode>2): Likewise.
> (xsrdpi<mode>): Add support for the lround function.
> (lround<mode>2): Likewise.
I would prefer that you reverse the meaning of "Fv" and "Fv2". "Fv"
corresponds to VSX2 and "Fv2" corresponds to VSX, which is confusing
for anyone trying to make sense of this in the future.
Also, the lround<mode>di2 pattern should use "Fv" not "wa" from my
original patch. And the ChangeLog entry should list lround<mode>di2.
Okay with those changes, after the cause of the SEGV is diagnosed and fixed.
Thanks, David
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-23 22:15 ` Michael Meissner
2015-11-24 0:06 ` David Edelsohn
@ 2015-11-24 0:16 ` Michael Meissner
1 sibling, 0 replies; 11+ messages in thread
From: Michael Meissner @ 2015-11-24 0:16 UTC (permalink / raw)
To: Michael Meissner, David Edelsohn, Richard Biener,
Segher Boessenkool, William J. Schmidt, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 1359 bytes --]
Segher Boessenkool reminded me that the lround define_expand should not have
the wa and =d constraints. This patch fixes that problem. The little endian
power8 system has passed the bootstrap and make check tests.
The big endian power7 system is chugging away on the stage2 build if I use a
more recent compiler than the host compiler (both trunk without the patches and
with the patches failed in the same way). Obviously we need to dig into that
failure.
2015-11-23 David Edelsohn <dje.gcc@gmail.com>
Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec.
(Fv2): New mode attribute to be used when ISA 2.06 instructions
are used on SF/DF values.
(abs<mode>2_fpr): Use <Fv2> instead of <Fv>.
(nabs<mode>2_fpr): Likewise.
(neg<mode>2_fpr): Likewise.
(copysign<mode>3_fcpsgn): Likewise.
(smax<mode>3_vsx): Likewise.
(smin<mode>3_vsx): Likewise.
(floatsi<mode>2_lfiwax): Likewise.
(floatunssi<mode>2_lfiwz): Likewise.
(fctiwz_<mode>): Likewise.
(fctiwuz_<mode>): Likewise.
(btrunc<mode>2): Likewise.
(ceil<mode>2): Likewise.
(floor<mode>2): Likewise.
(xsrdpi<mode>): Add support for the lround function.
(lround<mode>2): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: lround.patch02b --]
[-- Type: text/plain, Size: 8425 bytes --]
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 230768)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -77,6 +77,7 @@ (define_c_enum "unspec"
UNSPEC_FRIN
UNSPEC_FRIP
UNSPEC_FRIZ
+ UNSPEC_XSRDPI
UNSPEC_LD_MPIC ; load_macho_picbase
UNSPEC_RELD_MPIC ; re-load_macho_picbase
UNSPEC_MPIC_CORRECT ; macho_correct_pic
@@ -491,9 +492,17 @@ (define_mode_attr Fvsx [(SF "sp") (DF "
; SF/DF constraint for arithmetic on traditional floating point registers
(define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
-; SF/DF constraint for arithmetic on VSX registers
+; SF/DF constraint for arithmetic on VSX registers. This is intended to be
+; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
+; instructions added in ISA 2.07 (power8)
(define_mode_attr Fv [(SF "wy") (DF "ws") (DI "wi")])
+; SF/DF constraint for arithmetic on VSX registers using instructions added in
+; ISA 2.06 (power7). This includes instructions that normally target DF mode,
+; but are used on SFmode, since internally SFmode values are kept in the DFmode
+; format.
+(define_mode_attr Fv2 [(SF "ww") (DF "ws") (DI "wi")])
+
; SF/DF constraint for arithmetic on altivec registers
(define_mode_attr Fa [(SF "wu") (DF "wv")])
@@ -4299,8 +4308,8 @@ (define_expand "abs<mode>2"
"")
(define_insn "*abs<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fabs %0,%1
@@ -4309,10 +4318,10 @@ (define_insn "*abs<mode>2_fpr"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "*nabs<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
(neg:SFDF
(abs:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>"))))]
"TARGET_<MODE>_FPR"
"@
fnabs %0,%1
@@ -4327,8 +4336,8 @@ (define_expand "neg<mode>2"
"")
(define_insn "*neg<mode>2_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fneg %0,%1
@@ -4557,9 +4566,9 @@ (define_expand "copysign<mode>3"
;; Use an unspec rather providing an if-then-else in RTL, to prevent the
;; compiler from optimizing -0.0
(define_insn "copysign<mode>3_fcpsgn"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_COPYSIGN))]
"TARGET_<MODE>_FPR && TARGET_CMPB"
"@
@@ -4593,9 +4602,9 @@ (define_expand "smax<mode>3"
})
(define_insn "*smax<mode>3_vsx"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR && TARGET_VSX"
"xsmaxdp %x0,%x1,%x2"
[(set_attr "type" "fp")])
@@ -4613,9 +4622,9 @@ (define_expand "smin<mode>3"
})
(define_insn "*smin<mode>3_vsx"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR && TARGET_VSX"
"xsmindp %x0,%x1,%x2"
[(set_attr "type" "fp")])
@@ -4836,7 +4845,7 @@ (define_insn "lfiwax"
; not be needed and also in case the insns are deleted as dead code.
(define_insn_and_split "floatsi<mode>2_lfiwax"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv2>")
(float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wj"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX
@@ -4911,7 +4920,7 @@ (define_insn "lfiwzx"
[(set_attr "type" "fpload,fpload,mftgpr")])
(define_insn_and_split "floatunssi<mode>2_lfiwzx"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv2>")
(unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r")))
(clobber (match_scratch:DI 2 "=wj"))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX
@@ -5346,7 +5355,7 @@ (define_insn "*fixuns_trunc<mode>di2_fct
; before the instruction.
(define_insn "fctiwz_<mode>"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
- (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
+ (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>"))]
UNSPEC_FCTIWZ))]
"TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT"
"@
@@ -5357,7 +5366,7 @@ (define_insn "fctiwz_<mode>"
(define_insn "fctiwuz_<mode>"
[(set (match_operand:DI 0 "gpc_reg_operand" "=d,wi")
(unspec:DI [(unsigned_fix:SI
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>"))]
UNSPEC_FCTIWUZ))]
"TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ"
"@
@@ -5458,8 +5467,8 @@ (define_insn "lrint<mode>di2"
[(set_attr "type" "fp")])
(define_insn "btrunc<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_FRIZ))]
"TARGET_<MODE>_FPR && TARGET_FPRND"
"@
@@ -5469,8 +5478,8 @@ (define_insn "btrunc<mode>2"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "ceil<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_FRIP))]
"TARGET_<MODE>_FPR && TARGET_FPRND"
"@
@@ -5480,8 +5489,8 @@ (define_insn "ceil<mode>2"
(set_attr "fp_type" "fp_addsub_<Fs>")])
(define_insn "floor<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_FRIM))]
"TARGET_<MODE>_FPR && TARGET_FPRND"
"@
@@ -5500,6 +5509,27 @@ (define_insn "round<mode>2"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_<Fs>")])
+(define_insn "*xsrdpi<mode>2"
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Fv2>")]
+ UNSPEC_XSRDPI))]
+ "TARGET_<MODE>_FPR && TARGET_VSX"
+ "xsrdpi %x0,%x1"
+ [(set_attr "type" "fp")
+ (set_attr "fp_type" "fp_addsub_<Fs>")])
+
+(define_expand "lround<mode>di2"
+ [(set (match_dup 2)
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "")]
+ UNSPEC_XSRDPI))
+ (set (match_operand:DI 0 "gpc_reg_operand" "")
+ (unspec:DI [(match_dup 2)]
+ UNSPEC_FCTID))]
+ "TARGET_<MODE>_FPR && TARGET_VSX"
+{
+ operands[2] = gen_reg_rtx (<MODE>mode);
+})
+
; An UNSPEC is used so we don't have to support SImode in FP registers.
(define_insn "stfiwx"
[(set (match_operand:SI 0 "memory_operand" "=Z")
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-24 0:06 ` David Edelsohn
@ 2015-11-24 18:51 ` Michael Meissner
2015-11-24 19:00 ` Michael Meissner
2015-11-24 23:01 ` Michael Meissner
1 sibling, 1 reply; 11+ messages in thread
From: Michael Meissner @ 2015-11-24 18:51 UTC (permalink / raw)
To: David Edelsohn
Cc: Michael Meissner, Richard Biener, Segher Boessenkool,
William J. Schmidt, GCC Patches
[-- Attachment #1: Type: text/plain, Size: 1558 bytes --]
On Mon, Nov 23, 2015 at 07:04:33PM -0500, David Edelsohn wrote:
> I would prefer that you reverse the meaning of "Fv" and "Fv2". "Fv"
> corresponds to VSX2 and "Fv2" corresponds to VSX, which is confusing
> for anyone trying to make sense of this in the future.
>
> Also, the lround<mode>di2 pattern should use "Fv" not "wa" from my
> original patch. And the ChangeLog entry should list lround<mode>di2.
>
> Okay with those changes, after the cause of the SEGV is diagnosed and fixed.
I checked in the following patch. Note, the segfault is independent of the
patch. I will look into it shortly.
I will back port this patch to GCC 5 as we discussed.
2015-11-24 David Edelsohn <dje.gcc@gmail.com>
Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec.
(Fv2): New mode attribute to be used when ISA 2.06 instructions
are used on SF/DF values.
(abs<mode>2_fpr): Use <Fv2> instead of <Fv>.
(nabs<mode>2_fpr): Likewise.
(neg<mode>2_fpr): Likewise.
(copysign<mode>3_fcpsgn): Likewise.
(smax<mode>3_vsx): Likewise.
(smin<mode>3_vsx): Likewise.
(floatsi<mode>2_lfiwax): Likewise.
(floatunssi<mode>2_lfiwz): Likewise.
(fctiwz_<mode>): Likewise.
(fctiwuz_<mode>): Likewise.
(btrunc<mode>2): Likewise.
(ceil<mode>2): Likewise.
(floor<mode>2): Likewise.
(xsrdpi<mode>): Add support for the lround function.
(lround<mode>di2): Likewise.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
[-- Attachment #2: lround.patch03b --]
[-- Type: text/plain, Size: 9110 bytes --]
Index: gcc/config/rs6000/rs6000.md
===================================================================
--- gcc/config/rs6000/rs6000.md (revision 230768)
+++ gcc/config/rs6000/rs6000.md (working copy)
@@ -77,6 +77,7 @@ (define_c_enum "unspec"
UNSPEC_FRIN
UNSPEC_FRIP
UNSPEC_FRIZ
+ UNSPEC_XSRDPI
UNSPEC_LD_MPIC ; load_macho_picbase
UNSPEC_RELD_MPIC ; re-load_macho_picbase
UNSPEC_MPIC_CORRECT ; macho_correct_pic
@@ -491,8 +492,16 @@ (define_mode_attr Fvsx [(SF "sp") (DF "
; SF/DF constraint for arithmetic on traditional floating point registers
(define_mode_attr Ff [(SF "f") (DF "d") (DI "d")])
-; SF/DF constraint for arithmetic on VSX registers
-(define_mode_attr Fv [(SF "wy") (DF "ws") (DI "wi")])
+; SF/DF constraint for arithmetic on VSX registers using instructions added in
+; ISA 2.06 (power7). This includes instructions that normally target DF mode,
+; but are used on SFmode, since internally SFmode values are kept in the DFmode
+; format.
+(define_mode_attr Fv [(SF "ww") (DF "ws") (DI "wi")])
+
+; SF/DF constraint for arithmetic on VSX registers. This is intended to be
+; used for DFmode instructions added in ISA 2.06 (power7) and SFmode
+; instructions added in ISA 2.07 (power8)
+(define_mode_attr Fv2 [(SF "wy") (DF "ws") (DI "wi")])
; SF/DF constraint for arithmetic on altivec registers
(define_mode_attr Fa [(SF "wu") (DF "wv")])
@@ -4344,9 +4353,9 @@ (define_expand "add<mode>3"
"")
(define_insn "*add<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fadd<Ftrad> %0,%1,%2
@@ -4362,9 +4371,9 @@ (define_expand "sub<mode>3"
"")
(define_insn "*sub<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fsub<Ftrad> %0,%1,%2
@@ -4380,9 +4389,9 @@ (define_expand "mul<mode>3"
"")
(define_insn "*mul<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fmul<Ftrad> %0,%1,%2
@@ -4398,9 +4407,9 @@ (define_expand "div<mode>3"
"")
(define_insn "*div<mode>3_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU"
"@
fdiv<Ftrad> %0,%1,%2
@@ -4409,8 +4418,8 @@ (define_insn "*div<mode>3_fpr"
(set_attr "fp_type" "fp_div_<Fs>")])
(define_insn "sqrt<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU
&& (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))"
"@
@@ -4421,8 +4430,8 @@ (define_insn "sqrt<mode>2"
;; Floating point reciprocal approximation
(define_insn "fre<Fs>"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_FRES))]
"TARGET_<FFRE>"
"@
@@ -4431,8 +4440,8 @@ (define_insn "fre<Fs>"
[(set_attr "type" "fp")])
(define_insn "*rsqrt<mode>2"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>")
- (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")]
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")]
UNSPEC_RSQRT))]
"RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)"
"@
@@ -4443,8 +4452,8 @@ (define_insn "*rsqrt<mode>2"
;; Floating point comparisons
(define_insn "*cmp<mode>_fpr"
[(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y")
- (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))]
+ (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fcmpu %0,%1,%2
@@ -5500,6 +5509,27 @@ (define_insn "round<mode>2"
[(set_attr "type" "fp")
(set_attr "fp_type" "fp_addsub_<Fs>")])
+(define_insn "*xsrdpi<mode>2"
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Fv>")
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Fv>")]
+ UNSPEC_XSRDPI))]
+ "TARGET_<MODE>_FPR && TARGET_VSX"
+ "xsrdpi %x0,%x1"
+ [(set_attr "type" "fp")
+ (set_attr "fp_type" "fp_addsub_<Fs>")])
+
+(define_expand "lround<mode>di2"
+ [(set (match_dup 2)
+ (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "wa")]
+ UNSPEC_XSRDPI))
+ (set (match_operand:DI 0 "gpc_reg_operand" "=d")
+ (unspec:DI [(match_dup 2)]
+ UNSPEC_FCTID))]
+ "TARGET_<MODE>_FPR && TARGET_VSX"
+{
+ operands[2] = gen_reg_rtx (<MODE>mode);
+})
+
; An UNSPEC is used so we don't have to support SImode in FP registers.
(define_insn "stfiwx"
[(set (match_operand:SI 0 "memory_operand" "=Z")
@@ -12468,11 +12498,11 @@ (define_expand "fma<mode>4"
"")
(define_insn "*fma<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv2>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))]
"TARGET_<MODE>_FPR"
"@
fmadd<Ftrad> %0,%1,%2,%3
@@ -12492,11 +12522,11 @@ (define_expand "fms<mode>4"
"")
(define_insn "*fms<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
- (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
+ (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))]
"TARGET_<MODE>_FPR"
"@
fmsub<Ftrad> %0,%1,%2,%3
@@ -12539,12 +12569,12 @@ (define_expand "nfma<mode>4"
"")
(define_insn "*nfma<mode>4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
(neg:SFDF
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))]
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>"))))]
"TARGET_<MODE>_FPR"
"@
fnmadd<Ftrad> %0,%1,%2,%3
@@ -12565,13 +12595,13 @@ (define_expand "nfms<mode>4"
"")
(define_insn "*nfmssf4_fpr"
- [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>")
+ [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv2>,<Fv2>")
(neg:SFDF
(fma:SFDF
- (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>")
- (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0")
+ (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv2>,<Fv2>")
+ (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv2>,0")
(neg:SFDF
- (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))]
+ (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv2>")))))]
"TARGET_<MODE>_FPR"
"@
fnmsub<Ftrad> %0,%1,%2,%3
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-24 18:51 ` Michael Meissner
@ 2015-11-24 19:00 ` Michael Meissner
2015-11-24 19:29 ` David Edelsohn
0 siblings, 1 reply; 11+ messages in thread
From: Michael Meissner @ 2015-11-24 19:00 UTC (permalink / raw)
To: Michael Meissner, David Edelsohn, Richard Biener,
Segher Boessenkool, William J. Schmidt, GCC Patches
Whoops, I forgot to update the ChangeLog after reversing Fv and Fv2.
2015-11-24 David Edelsohn <dje.gcc@gmail.com>
Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec.
(Fv2): New mode attribute to be used when ISA 2.07 instructions
are used on SF values, and ISA 2.06 instructions on DF values.
(add<mode>3_fpr): Use <Fv2> instead of <Fv>.
(sub<mode>3_fpr): Use <Fv2> instead of <Fv>.
(mul<mode>3_fpr): Use <Fv2> instead of <Fv>.
(div<mode>3_fpr): Use <Fv2> instead of <Fv>.
(sqrt<mode>2): Use <Fv2> instead of <Fv>.
(fre<Fs>): Use <Fv2> instead of <Fv>.
(rsqrt<mode>2): Use <Fv2> instead of <Fv>.
(cmp<mode>_fpr): Use <Fv2> instead of <Fv>.
(xsrdpi<mode>): Add support for the lround function.
(lround<mode>di2): Likewise.
(fma<mode>4_fpr): Use <Fv2> instead of <Fv>.
(fms<mode>4_fpr): Use <Fv2> instead of <Fv>.
(nfma<mode>4_fpr): Use <Fv2> instead of <Fv>.
(nfms<mode>4_fpr): Use <Fv2> instead of <Fv>.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-24 19:00 ` Michael Meissner
@ 2015-11-24 19:29 ` David Edelsohn
0 siblings, 0 replies; 11+ messages in thread
From: David Edelsohn @ 2015-11-24 19:29 UTC (permalink / raw)
To: Michael Meissner, Richard Biener, Segher Boessenkool,
William J. Schmidt, GCC Patches
On Tue, Nov 24, 2015 at 1:55 PM, Michael Meissner
<meissner@linux.vnet.ibm.com> wrote:
> Whoops, I forgot to update the ChangeLog after reversing Fv and Fv2.
>
> 2015-11-24 David Edelsohn <dje.gcc@gmail.com>
> Michael Meissner <meissner@linux.vnet.ibm.com>
>
> * config/rs6000/rs6000.md (UNSPEC_XSRDPI): New unspec.
> (Fv2): New mode attribute to be used when ISA 2.07 instructions
> are used on SF values, and ISA 2.06 instructions on DF values.
> (add<mode>3_fpr): Use <Fv2> instead of <Fv>.
> (sub<mode>3_fpr): Use <Fv2> instead of <Fv>.
> (mul<mode>3_fpr): Use <Fv2> instead of <Fv>.
> (div<mode>3_fpr): Use <Fv2> instead of <Fv>.
> (sqrt<mode>2): Use <Fv2> instead of <Fv>.
> (fre<Fs>): Use <Fv2> instead of <Fv>.
> (rsqrt<mode>2): Use <Fv2> instead of <Fv>.
Why are the above instructions converted to Fv2? xsadd, xssub, xsmul,
xsdiv, xsre, and xsrsqrte are Power7 instructions.
xssqrt and the ones below are Power8.
> (cmp<mode>_fpr): Use <Fv2> instead of <Fv>.
> (xsrdpi<mode>): Add support for the lround function.
> (lround<mode>di2): Likewise.
> (fma<mode>4_fpr): Use <Fv2> instead of <Fv>.
> (fms<mode>4_fpr): Use <Fv2> instead of <Fv>.
> (nfma<mode>4_fpr): Use <Fv2> instead of <Fv>.
> (nfms<mode>4_fpr): Use <Fv2> instead of <Fv>.
Thanks, David
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] lround for PowerPC
2015-11-24 0:06 ` David Edelsohn
2015-11-24 18:51 ` Michael Meissner
@ 2015-11-24 23:01 ` Michael Meissner
1 sibling, 0 replies; 11+ messages in thread
From: Michael Meissner @ 2015-11-24 23:01 UTC (permalink / raw)
To: David Edelsohn
Cc: Michael Meissner, Richard Biener, Segher Boessenkool,
William J. Schmidt, GCC Patches
On Mon, Nov 23, 2015 at 07:04:33PM -0500, David Edelsohn wrote:
> Okay with those changes, after the cause of the SEGV is diagnosed and fixed.
It must have a temporary failure (either in the source, or perhaps something
was amiss on the machine I was building on). I checked out a new trunk, and
bootstrapped it with the host compiler, and it no longer fails.
--
Michael Meissner, IBM
IBM, M/S 2506R, 550 King Street, Littleton, MA 01460-6245, USA
email: meissner@linux.vnet.ibm.com, phone: +1 (978) 899-4797
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2015-11-24 22:43 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-11-22 3:21 [PATCH] lround for PowerPC David Edelsohn
2015-11-22 8:51 ` Richard Biener
2015-11-22 14:39 ` David Edelsohn
2015-11-22 20:58 ` David Edelsohn
2015-11-23 22:15 ` Michael Meissner
2015-11-24 0:06 ` David Edelsohn
2015-11-24 18:51 ` Michael Meissner
2015-11-24 19:00 ` Michael Meissner
2015-11-24 19:29 ` David Edelsohn
2015-11-24 23:01 ` Michael Meissner
2015-11-24 0:16 ` Michael Meissner
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