* [PATCH] RISC-V: Add missing vsetvl instruction type.
@ 2022-10-10 13:43 juzhe.zhong
2022-10-11 2:35 ` Kito Cheng
0 siblings, 1 reply; 2+ messages in thread
From: juzhe.zhong @ 2022-10-10 13:43 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
When implementing built-in framework, I notice I missed
vsetvl instruction type, so add it in a single patch
preparing for the following patches.
gcc/ChangeLog:
* config/riscv/riscv.md: Add vsetvl instruction type.
---
gcc/config/riscv/riscv.md | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 014206fb8bd..2d1cda2b98f 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -229,6 +229,7 @@
;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
;; rdvlenb vector byte length vlenb csrr read
;; rdvl vector length vl csrr read
+;; vsetvl vector configuration-setting instrucions
;; 7. Vector Loads and Stores
;; vlde vector unit-stride load instructions
;; vste vector unit-stride store instructions
@@ -316,7 +317,7 @@
"unknown,branch,jump,call,load,fpload,store,fpstore,
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
- rdvlenb,rdvl,vlde,vste,vldm,vstm,vlds,vsts,
+ rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
--
2.36.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH] RISC-V: Add missing vsetvl instruction type.
2022-10-10 13:43 [PATCH] RISC-V: Add missing vsetvl instruction type juzhe.zhong
@ 2022-10-11 2:35 ` Kito Cheng
0 siblings, 0 replies; 2+ messages in thread
From: Kito Cheng @ 2022-10-11 2:35 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches
Committed, thanks :)
On Mon, Oct 10, 2022 at 9:44 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> When implementing built-in framework, I notice I missed
> vsetvl instruction type, so add it in a single patch
> preparing for the following patches.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add vsetvl instruction type.
>
> ---
> gcc/config/riscv/riscv.md | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 014206fb8bd..2d1cda2b98f 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -229,6 +229,7 @@
> ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
> ;; rdvlenb vector byte length vlenb csrr read
> ;; rdvl vector length vl csrr read
> +;; vsetvl vector configuration-setting instrucions
> ;; 7. Vector Loads and Stores
> ;; vlde vector unit-stride load instructions
> ;; vste vector unit-stride store instructions
> @@ -316,7 +317,7 @@
> "unknown,branch,jump,call,load,fpload,store,fpstore,
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
> - rdvlenb,rdvl,vlde,vste,vldm,vstm,vlds,vsts,
> + rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
> vldux,vldox,vstux,vstox,vldff,vldr,vstr,
> vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
> vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
> --
> 2.36.1
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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