From: Segher Boessenkool <segher@kernel.crashing.org>
To: "Jiang, Haochen" <haochen.jiang@intel.com>
Cc: Andrew Pinski <pinskia@gmail.com>,
"gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org>,
"aoliva@gcc.gnu.org" <aoliva@gcc.gnu.org>,
"richard.sandiford@arm.com" <richard.sandiford@arm.com>,
"uweigand@de.ibm.com" <uweigand@de.ibm.com>,
"linkw@gcc.gnu.org" <linkw@gcc.gnu.org>,
"gnu@amylaar.uk" <gnu@amylaar.uk>,
"dje.gcc@gmail.com" <dje.gcc@gmail.com>,
"olegendo@gcc.gnu.org" <olegendo@gcc.gnu.org>,
"claziss@synopsys.com" <claziss@synopsys.com>,
"mfortune@gmail.com" <mfortune@gmail.com>,
"davem@redhat.com" <davem@redhat.com>,
"dave.anglin@bell.net" <dave.anglin@bell.net>,
"hubicka@ucw.cz" <hubicka@ucw.cz>,
"richard.earnshaw@arm.com" <richard.earnshaw@arm.com>,
"rguenther@suse.de" <rguenther@suse.de>,
"marcus.shawcroft@arm.com" <marcus.shawcroft@arm.com>,
"ramana.radhakrishnan@arm.com" <ramana.radhakrishnan@arm.com>,
"Liu, Hongtao" <hongtao.liu@intel.com>
Subject: Re: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM
Date: Thu, 20 Oct 2022 12:25:58 -0500 [thread overview]
Message-ID: <20221020172558.GS25951@gate.crashing.org> (raw)
In-Reply-To: <SA1PR11MB59461A4D35F45E65A67A669EEC2A9@SA1PR11MB5946.namprd11.prod.outlook.com>
On Thu, Oct 20, 2022 at 01:44:15AM +0000, Jiang, Haochen wrote:
> Maybe the testcase change cause some misunderstanding and concern.
>
> Actually, the patch did not disrupt the previous builtins, as the builtin_prefetch
> uses vargs. I set the default value of the new parameter as data prefetch, which
> means that if we are not using the fourth parameter, just like how we use
> prefetch previously, it is still what it is.
I still think it is a mistake to have one builtin do two very distinct
operations, only very superficially related. Instruction fetch and data
demand loads are almosty entirely unrelated, and so is the prefetch
machinery for them, on all machines I am familiar with. Which makes
sense anyway, since instruction prefetch and data prefetch have
completely different performance characteristics and considerations.
Maybe if you start with the mistake of having unified L1 caches it
seems natural, but thankfully most machines do not do that.
Segher
next prev parent reply other threads:[~2022-10-20 17:27 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-14 8:34 [PATCH 0/2] Add a Fourth parameter for prefetch and Support Intel PREFETCHI Haochen Jiang
2022-10-14 8:34 ` [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM Haochen Jiang
2022-10-14 8:46 ` Hongtao Liu
2022-10-17 15:28 ` Richard Earnshaw
2022-10-18 9:20 ` [PATCH v2] " Haochen Jiang
2022-10-19 17:14 ` [PATCH 1/2] " Andrew Pinski
2022-10-19 21:14 ` Segher Boessenkool
2022-10-20 1:27 ` Hongtao Liu
2022-10-20 1:44 ` Jiang, Haochen
2022-10-20 17:25 ` Segher Boessenkool [this message]
2022-10-20 17:37 ` Andrew Pinski
2022-10-21 10:17 ` Richard Earnshaw
2022-10-21 18:08 ` Segher Boessenkool
2022-10-19 21:06 ` Segher Boessenkool
2022-10-20 1:39 ` Hongtao Liu
2022-10-20 3:12 ` Hongtao Liu
2022-10-20 18:44 ` Segher Boessenkool
2022-10-20 7:34 ` Jiang, Haochen
2022-10-20 18:54 ` Segher Boessenkool
2022-10-21 3:17 ` Jiang, Haochen
2022-10-24 10:00 ` Richard Sandiford
2022-10-24 21:19 ` Segher Boessenkool
2022-10-14 8:34 ` [PATCH 2/2] Support Intel prefetchit0/t1 Haochen Jiang
2022-10-20 3:45 ` H.J. Lu
2022-10-20 4:04 ` Hongtao Liu
2022-10-19 20:49 ` [PATCH 0/2] Add a Fourth parameter for prefetch and Support Intel PREFETCHI Segher Boessenkool
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