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From: Hongtao Liu <crazylht@gmail.com>
To: Segher Boessenkool <segher@kernel.crashing.org>
Cc: Haochen Jiang <haochen.jiang@intel.com>,
	aoliva@gcc.gnu.org, richard.sandiford@arm.com,
	 uweigand@de.ibm.com, linkw@gcc.gnu.org, gnu@amylaar.uk,
	dje.gcc@gmail.com,  olegendo@gcc.gnu.org, claziss@synopsys.com,
	mfortune@gmail.com,  gcc-patches@gcc.gnu.org, davem@redhat.com,
	dave.anglin@bell.net,  hubicka@ucw.cz, richard.earnshaw@arm.com,
	rguenther@suse.de,  marcus.shawcroft@arm.com,
	ramana.radhakrishnan@arm.com, hongtao.liu@intel.com
Subject: Re: [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM
Date: Thu, 20 Oct 2022 09:39:52 +0800	[thread overview]
Message-ID: <CAMZc-bzAzTQaeuVZ31WpyknG2NnHcHwsHDx8pGatHQfzLzTRqA@mail.gmail.com> (raw)
In-Reply-To: <20221019210645.GP25951@gate.crashing.org>

On Thu, Oct 20, 2022 at 5:08 AM Segher Boessenkool
<segher@kernel.crashing.org> wrote:
>
> On Fri, Oct 14, 2022 at 04:34:05PM +0800, Haochen Jiang wrote:
> >       * config/s390/s390.cc (s390_expand_cpymem): Generate fourth parameter for
>
> (Many too long lines here, this is the first one.  Changelog lines are
> max. 80 positions; a tab is eight).
>
> > +  /* Argument 3 must be either zero or one.  */
> > +  if (INTVAL (op3) != 0 && INTVAL (op3) != 1)
> > +    {
> > +      warning (0, "invalid fourth argument to %<__builtin_prefetch%>;"
> > +     " using one");
>
> "using 1" makes sense maybe, but "using one" reads as "using an
> argument", not very sane.
>
> An error would be better here anyway?
>
> > --- a/gcc/config/rs6000/rs6000.md
> > +++ b/gcc/config/rs6000/rs6000.md
> > @@ -14060,10 +14060,25 @@
> >    DONE;
> >  })
> >
> > -(define_insn "prefetch"
> > +(define_expand "prefetch"
> > +  [(prefetch (match_operand 0 "indexed_or_indirect_address")
> > +          (match_operand:SI 1 "const_int_operand")
> > +          (match_operand:SI 2 "const_int_operand")
> > +          (match_operand:SI 3 "const_int_operand"))]
> > +  ""
> > +{
> > +  if (INTVAL (operands[3]) == 0)
> > +  {
>
> Broken indentation.
>
> > +    warning (0, "instruction prefetch is not supported; using data prefetch");
>
> Please use a separate pattern for this, and leave prefetch to mean data
> prefetch, as documented!  Documentation you didn't change btw.  Call the
> new one instruction_prefetch or something equally boring maybe :-)
>
> When you send an updated patch, please split it up better?  Generic
> changes and documentation in one patch, target changes in a separate
We'll split testcase into a separate patch.
> patch or patches, and testsuite is distinct as well.  It isn't nice to
> have to scroll through thousands of lines to see if there is anything
> relevant to you.

Yes, it's an inconvenience for review, sorry for that. But since we've
changed rtl def for prefetch, moving the general part into a separate
commit may break bootstrap when rtl-check is enabled.
-DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
+DEF_RTL_EXPR(PREFETCH, "prefetch", "eeee", RTX_EXTRA)

And we want to make each commit pass the bootstrap and regression test.
>
> Thanks,
>
>
> Segher



-- 
BR,
Hongtao

  reply	other threads:[~2022-10-20  1:40 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-10-14  8:34 [PATCH 0/2] Add a Fourth parameter for prefetch and Support Intel PREFETCHI Haochen Jiang
2022-10-14  8:34 ` [PATCH 1/2] Add a parameter for the builtin function of prefetch to align with LLVM Haochen Jiang
2022-10-14  8:46   ` Hongtao Liu
2022-10-17 15:28   ` Richard Earnshaw
2022-10-18  9:20     ` [PATCH v2] " Haochen Jiang
2022-10-19 17:14   ` [PATCH 1/2] " Andrew Pinski
2022-10-19 21:14     ` Segher Boessenkool
2022-10-20  1:27       ` Hongtao Liu
2022-10-20  1:44       ` Jiang, Haochen
2022-10-20 17:25         ` Segher Boessenkool
2022-10-20 17:37           ` Andrew Pinski
2022-10-21 10:17             ` Richard Earnshaw
2022-10-21 18:08               ` Segher Boessenkool
2022-10-19 21:06   ` Segher Boessenkool
2022-10-20  1:39     ` Hongtao Liu [this message]
2022-10-20  3:12       ` Hongtao Liu
2022-10-20 18:44         ` Segher Boessenkool
2022-10-20  7:34     ` Jiang, Haochen
2022-10-20 18:54       ` Segher Boessenkool
2022-10-21  3:17         ` Jiang, Haochen
2022-10-24 10:00         ` Richard Sandiford
2022-10-24 21:19           ` Segher Boessenkool
2022-10-14  8:34 ` [PATCH 2/2] Support Intel prefetchit0/t1 Haochen Jiang
2022-10-20  3:45   ` H.J. Lu
2022-10-20  4:04     ` Hongtao Liu
2022-10-19 20:49 ` [PATCH 0/2] Add a Fourth parameter for prefetch and Support Intel PREFETCHI Segher Boessenkool

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