From: juzhe.zhong@rivai.ai
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com, pinskia@gmail.com,
Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
Subject: [PATCH] RISC-V: Support (set (mem) (const_poly_int))
Date: Mon, 24 Oct 2022 10:27:37 +0800 [thread overview]
Message-ID: <20221024022737.52627-1-juzhe.zhong@rivai.ai> (raw)
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Adjust using force_reg.
---
gcc/config/riscv/riscv.cc | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 98374a922d1..1fd34f6ae8d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1967,9 +1967,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
*/
if (MEM_P (dest))
{
- rtx tmp = gen_reg_rtx (mode);
- emit_move_insn (tmp, src);
- emit_move_insn (dest, tmp);
+ emit_move_insn (dest, force_reg (mode, src));
return true;
}
poly_int64 value = rtx_to_poly_int64 (src);
--
2.36.1
next reply other threads:[~2022-10-24 2:27 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-10-24 2:27 juzhe.zhong [this message]
2022-10-24 2:50 ` Kito Cheng
-- strict thread matches above, loose matches on Subject: below --
2022-10-24 2:03 juzhe.zhong
2022-10-24 2:14 ` Andrew Pinski
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