* [PATCH] RISC-V: Support (set (mem) (const_poly_int))
@ 2022-10-24 2:27 juzhe.zhong
2022-10-24 2:50 ` Kito Cheng
0 siblings, 1 reply; 4+ messages in thread
From: juzhe.zhong @ 2022-10-24 2:27 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, pinskia, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Adjust using force_reg.
---
gcc/config/riscv/riscv.cc | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 98374a922d1..1fd34f6ae8d 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1967,9 +1967,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
*/
if (MEM_P (dest))
{
- rtx tmp = gen_reg_rtx (mode);
- emit_move_insn (tmp, src);
- emit_move_insn (dest, tmp);
+ emit_move_insn (dest, force_reg (mode, src));
return true;
}
poly_int64 value = rtx_to_poly_int64 (src);
--
2.36.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))
2022-10-24 2:27 [PATCH] RISC-V: Support (set (mem) (const_poly_int)) juzhe.zhong
@ 2022-10-24 2:50 ` Kito Cheng
0 siblings, 0 replies; 4+ messages in thread
From: Kito Cheng @ 2022-10-24 2:50 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches
Merged two changes into one patch, and committed to master :)
On Mon, Oct 24, 2022 at 10:28 AM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Adjust using force_reg.
>
> ---
> gcc/config/riscv/riscv.cc | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 98374a922d1..1fd34f6ae8d 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1967,9 +1967,7 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
> */
> if (MEM_P (dest))
> {
> - rtx tmp = gen_reg_rtx (mode);
> - emit_move_insn (tmp, src);
> - emit_move_insn (dest, tmp);
> + emit_move_insn (dest, force_reg (mode, src));
> return true;
> }
> poly_int64 value = rtx_to_poly_int64 (src);
> --
> 2.36.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH] RISC-V: Support (set (mem) (const_poly_int))
@ 2022-10-24 2:03 juzhe.zhong
2022-10-24 2:14 ` Andrew Pinski
0 siblings, 1 reply; 4+ messages in thread
From: juzhe.zhong @ 2022-10-24 2:03 UTC (permalink / raw)
To: gcc-patches; +Cc: kito.cheng, palmer, Ju-Zhe Zhong
From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).
---
gcc/config/riscv/riscv.cc | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index 90a39047dd7..f7694ba043c 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
{
if (CONST_POLY_INT_P (src))
{
+ /*
+ Handle:
+ (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
+ (const_int 96 [0x60])) [0 S1 A8])
+ (const_poly_int:QI [8, 8]))
+ "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
+ */
+ if (MEM_P (dest))
+ {
+ rtx tmp = gen_reg_rtx (mode);
+ emit_move_insn (tmp, src);
+ emit_move_insn (dest, tmp);
+ return true;
+ }
poly_int64 value = rtx_to_poly_int64 (src);
if (!value.is_constant () && !TARGET_VECTOR)
{
--
2.36.1
^ permalink raw reply [flat|nested] 4+ messages in thread* Re: [PATCH] RISC-V: Support (set (mem) (const_poly_int))
2022-10-24 2:03 juzhe.zhong
@ 2022-10-24 2:14 ` Andrew Pinski
0 siblings, 0 replies; 4+ messages in thread
From: Andrew Pinski @ 2022-10-24 2:14 UTC (permalink / raw)
To: juzhe.zhong; +Cc: gcc-patches, kito.cheng
On Sun, Oct 23, 2022 at 7:04 PM <juzhe.zhong@rivai.ai> wrote:
>
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_legitimize_move): Support (set (mem) (const_poly_int)).
>
> ---
> gcc/config/riscv/riscv.cc | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index 90a39047dd7..f7694ba043c 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -1958,6 +1958,20 @@ riscv_legitimize_move (machine_mode mode, rtx dest, rtx src)
> {
> if (CONST_POLY_INT_P (src))
> {
> + /*
> + Handle:
> + (insn 183 182 184 6 (set (mem:QI (plus:DI (reg/f:DI 156)
> + (const_int 96 [0x60])) [0 S1 A8])
> + (const_poly_int:QI [8, 8]))
> + "../../../../riscv-gcc/libgcc/unwind-dw2.c":1579:3 -1 (nil))
> + */
> + if (MEM_P (dest))
> + {
> + rtx tmp = gen_reg_rtx (mode);
> + emit_move_insn (tmp, src);
> + emit_move_insn (dest, tmp);
Couldn't you just use force_reg here instead of the above?
Something like:
emit_move_insn (dest, force_reg (mode, src));
Thanks,
Andrew Pinski
> + return true;
> + }
> poly_int64 value = rtx_to_poly_int64 (src);
> if (!value.is_constant () && !TARGET_VECTOR)
> {
> --
> 2.36.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
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