[PATCH 0/4] LoongArch: Add some floating-point operations

[PATCH 0/4] LoongArch: Add some floating-point operations

[Xi Ruoyao]

These patches allow to expand the following builtins to floating point
instructions for LoongArch:

- __builtin_rint{,f}
- __builtin_{l,ll}rint{,f}
- __builtin_{l,ll}floor{,f}
- __builtin_{l,ll}ceil{,f}
- __builtin_scalb{n,ln}{,f}
- __builtin_logb{,f}

Bootstrapped and regtested on loongarch64-linux-gnu.  And a modified
Glibc using the builtins for rint{,f}, {l,ll}rint{,f}, and logb{,f}
also survived Glibc test suite.

Please review ASAP because GCC 13 stage 1 will end on Nov. 13th.

Xi Ruoyao (4):
  LoongArch: Rename frint_<fmt> to rint<mode>2
  LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions
  LoongArch: Add fscaleb.{s,d} instructions as ldexp{sf,df}3
  LoongArch: Add flogb.{s,d} instructions and expand logb{sf,df}2

 gcc/config/loongarch/loongarch.md            | 89 +++++++++++++++++++-
 gcc/testsuite/gcc.target/loongarch/flogb.c   | 18 ++++
 gcc/testsuite/gcc.target/loongarch/frint.c   | 16 ++++
 gcc/testsuite/gcc.target/loongarch/fscaleb.c | 48 +++++++++++
 gcc/testsuite/gcc.target/loongarch/ftint.c   | 44 ++++++++++
 5 files changed, 211 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/flogb.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/frint.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/fscaleb.c
 create mode 100644 gcc/testsuite/gcc.target/loongarch/ftint.c

-- 
2.38.1

[PATCH 1/4] LoongArch: Rename frint_<fmt> to rint<mode>2

[Xi Ruoyao]

Use standard name so __builtin_rint{,f} can be expanded to one
instruction.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (frint_<fmt>): Rename to ..
	(rint<mode>2): .. this.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/frint.c: New test.
---
 gcc/config/loongarch/loongarch.md          |  4 ++--
 gcc/testsuite/gcc.target/loongarch/frint.c | 16 ++++++++++++++++
 2 files changed, 18 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/frint.c

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index bda34d0f3db..a14ab14ac24 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -2012,8 +2012,8 @@ (define_insn "lui_h_hi12"
   [(set_attr "type" "move")]
 )
 
-;; Convert floating-point numbers to integers
-(define_insn "frint_<fmt>"
+;; Round floating-point numbers to integers
+(define_insn "rint<mode>2"
   [(set (match_operand:ANYF 0 "register_operand" "=f")
 	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
 		      UNSPEC_FRINT))]
diff --git a/gcc/testsuite/gcc.target/loongarch/frint.c b/gcc/testsuite/gcc.target/loongarch/frint.c
new file mode 100644
index 00000000000..3ee6a8f973a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/frint.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-mdouble-float" } */
+/* { dg-final { scan-assembler "frint\\.s" } } */
+/* { dg-final { scan-assembler "frint\\.d" } } */
+
+double
+my_rint (double a)
+{
+  return __builtin_rint (a);
+}
+
+float
+my_rintf (float a)
+{
+  return __builtin_rintf (a);
+}
-- 
2.38.1

[PATCH 2/4] LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions

[Xi Ruoyao]

This allows to optimize the following builtins if -fno-math-errno:

- __builtin_lrint{,f}
- __builtin_lfloor{,f}
- __builtin_lceil{,f}

Inspired by
https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605287.html.

ANYFI is added so the compiler won't try ftint.l.s if -mfpu=32.  If we
simply used GPR here an ICE would be triggered with __builtin_lrintf
and -mfpu=32.

Note that the .w.{s,d} variants are not tested because we don't support
ILP32 for now.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (UNSPEC_FTINT): New unspec.
	(UNSPEC_FTINTRM): Likewise.
	(UNSPEC_FTINTRP): Likewise.
	(LRINT): New define_int_iterator.
	(lrint_pattern): New define_int_attr.
	(lrint_submenmonic): Likewise.
	(ANYFI): New define_mode_iterator.
	(lrint<ANYF><ANYFI>): New instruction template.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/ftint.c: New test.
---
 gcc/config/loongarch/loongarch.md          | 28 ++++++++++++++
 gcc/testsuite/gcc.target/loongarch/ftint.c | 44 ++++++++++++++++++++++
 2 files changed, 72 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/ftint.c

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index a14ab14ac24..35cef272060 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -38,6 +38,9 @@ (define_c_enum "unspec" [
   UNSPEC_FMAX
   UNSPEC_FMIN
   UNSPEC_FCOPYSIGN
+  UNSPEC_FTINT
+  UNSPEC_FTINTRM
+  UNSPEC_FTINTRP
 
   ;; Override return address for exception handling.
   UNSPEC_EH_RETURN
@@ -374,6 +377,11 @@ (define_mode_iterator QHWD [QI HI SI (DI "TARGET_64BIT")])
 (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
 			    (DF "TARGET_DOUBLE_FLOAT")])
 
+;; Iterator for fixed-point modes which can be hold by a hardware
+;; floating-point register.
+(define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT")
+			     (DI "TARGET_DOUBLE_FLOAT")])
+
 ;; A mode for which moves involving FPRs may need to be split.
 (define_mode_iterator SPLITF
   [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
@@ -515,6 +523,16 @@ (define_code_attr fcond [(unordered "cun")
 (define_code_attr sel [(eq "masknez") (ne "maskeqz")])
 (define_code_attr selinv [(eq "maskeqz") (ne "masknez")])
 
+;; Iterator and attributes for floating-point to fixed-point conversion
+;; instructions.
+(define_int_iterator LRINT [UNSPEC_FTINT UNSPEC_FTINTRM UNSPEC_FTINTRP])
+(define_int_attr lrint_pattern [(UNSPEC_FTINT "lrint")
+				(UNSPEC_FTINTRM "lfloor")
+				(UNSPEC_FTINTRP "lceil")])
+(define_int_attr lrint_submenmonic [(UNSPEC_FTINT "")
+				    (UNSPEC_FTINTRM "rm")
+				    (UNSPEC_FTINTRP "rp")])
+
 ;;
 ;;  ....................
 ;;
@@ -2022,6 +2040,16 @@ (define_insn "rint<mode>2"
   [(set_attr "type" "fcvt")
    (set_attr "mode" "<MODE>")])
 
+;; Convert floating-point numbers to integers
+(define_insn "<lrint_pattern><ANYF:mode><ANYFI:mode>2"
+  [(set (match_operand:ANYFI 0 "register_operand" "=f")
+	(unspec:ANYFI [(match_operand:ANYF 1 "register_operand" "f")]
+		      LRINT))]
+  "TARGET_HARD_FLOAT"
+  "ftint<lrint_submenmonic>.<ANYFI:ifmt>.<ANYF:fmt> %0,%1"
+  [(set_attr "type" "fcvt")
+   (set_attr "mode" "<ANYF:MODE>")])
+
 ;; Load the low word of operand 0 with operand 1.
 (define_insn "load_low<mode>"
   [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
diff --git a/gcc/testsuite/gcc.target/loongarch/ftint.c b/gcc/testsuite/gcc.target/loongarch/ftint.c
new file mode 100644
index 00000000000..9c3c3a8a756
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/ftint.c
@@ -0,0 +1,44 @@
+/* { dg-do compile } */
+/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno" } */
+/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */
+/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */
+/* { dg-final { scan-assembler "ftintrm\\.l\\.s" } } */
+/* { dg-final { scan-assembler "ftintrm\\.l\\.d" } } */
+/* { dg-final { scan-assembler "ftintrp\\.l\\.s" } } */
+/* { dg-final { scan-assembler "ftintrp\\.l\\.d" } } */
+
+long
+my_lrint (double a)
+{
+  return __builtin_lrint (a);
+}
+
+long
+my_lrintf (float a)
+{
+  return __builtin_lrintf (a);
+}
+
+long
+my_lfloor (double a)
+{
+  return __builtin_lfloor (a);
+}
+
+long
+my_lfloorf (float a)
+{
+  return __builtin_lfloorf (a);
+}
+
+long
+my_lceil (double a)
+{
+  return __builtin_lceil (a);
+}
+
+long
+my_lceilf (float a)
+{
+  return __builtin_lceilf (a);
+}
-- 
2.38.1

[PATCH 3/4] LoongArch: Add fscaleb.{s,d} instructions as ldexp{sf,df}3

[Xi Ruoyao]

This allows optimizing __builtin_ldexp{,f} and __builtin_scalbn{,f} with
-fno-math-errno.

IMODE is added because we can't hard code SI for operand 2: fscaleb.d
instruction always take the high half of both source registers into
account.  See my_ldexp_long in the test case.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (UNSPEC_FSCALEB): New unspec.
	(type): Add fscaleb.
	(IMODE): New mode attr.
	(ldexp<mode>3): New instruction template.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/fscaleb.c: New test.
---
 gcc/config/loongarch/loongarch.md            | 26 ++++++++++-
 gcc/testsuite/gcc.target/loongarch/fscaleb.c | 48 ++++++++++++++++++++
 2 files changed, 72 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/fscaleb.c

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 35cef272060..9070ac4e2f8 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -41,6 +41,7 @@ (define_c_enum "unspec" [
   UNSPEC_FTINT
   UNSPEC_FTINTRM
   UNSPEC_FTINTRP
+  UNSPEC_FSCALEB
 
   ;; Override return address for exception handling.
   UNSPEC_EH_RETURN
@@ -220,6 +221,7 @@ (define_attr "qword_mode" "no,yes"
 ;; fcmp		floating point compare
 ;; fcopysign	floating point copysign
 ;; fcvt		floating point convert
+;; fscaleb	floating point scale
 ;; fsqrt	floating point square root
 ;; frsqrt       floating point reciprocal square root
 ;; multi	multiword sequence (or user asm statements)
@@ -231,8 +233,8 @@ (define_attr "type"
   "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
    prefetch,prefetchx,condmove,mgtf,mftg,const,arith,logical,
    shift,slt,signext,clz,trap,imul,idiv,move,
-   fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fsqrt,
-   frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost"
+   fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fscaleb,
+   fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost"
   (cond [(eq_attr "jirl" "!unset") (const_string "call")
 	 (eq_attr "got" "load") (const_string "load")
 
@@ -418,6 +420,10 @@ (define_mode_attr UNITMODE [(SF "SF") (DF "DF")])
 ;; the controlling mode.
 (define_mode_attr HALFMODE [(DF "SI") (DI "SI") (TF "DI")])
 
+;; This attribute gives the integer mode that has the same size of a
+;; floating-point mode.
+(define_mode_attr IMODE [(SF "SI") (DF "DI")])
+
 ;; This code iterator allows signed and unsigned widening multiplications
 ;; to use the same template.
 (define_code_iterator any_extend [sign_extend zero_extend])
@@ -1011,7 +1017,23 @@ (define_insn "copysign<mode>3"
   "fcopysign.<fmt>\t%0,%1,%2"
   [(set_attr "type" "fcopysign")
    (set_attr "mode" "<UNITMODE>")])
+\f
+;;
+;;  ....................
+;;
+;;	FLOATING POINT SCALE
+;;
+;;  ....................
 
+(define_insn "ldexp<mode>3"
+  [(set (match_operand:ANYF 0 "register_operand" "=f")
+	(unspec:ANYF [(match_operand:ANYF    1 "register_operand" "f")
+		      (match_operand:<IMODE> 2 "register_operand" "f")]
+		     UNSPEC_FSCALEB))]
+  "TARGET_HARD_FLOAT"
+  "fscaleb.<fmt>\t%0,%1,%2"
+  [(set_attr "type" "fscaleb")
+   (set_attr "mode" "<UNITMODE>")])
 \f
 ;;
 ;;  ...................
diff --git a/gcc/testsuite/gcc.target/loongarch/fscaleb.c b/gcc/testsuite/gcc.target/loongarch/fscaleb.c
new file mode 100644
index 00000000000..f18470fbb8f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/fscaleb.c
@@ -0,0 +1,48 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -mabi=lp64d -mdouble-float -fno-math-errno" } */
+/* { dg-final { scan-assembler-times "fscaleb\\.s" 3 } } */
+/* { dg-final { scan-assembler-times "fscaleb\\.d" 4 } } */
+/* { dg-final { scan-assembler-times "slli\\.w" 1 } } */
+
+double
+my_scalbln (double a, long b)
+{
+  return __builtin_scalbln (a, b);
+}
+
+double
+my_scalbn (double a, int b)
+{
+  return __builtin_scalbn (a, b);
+}
+
+double
+my_ldexp (double a, int b)
+{
+  return __builtin_ldexp (a, b);
+}
+
+float
+my_scalblnf (float a, long b)
+{
+  return __builtin_scalblnf (a, b);
+}
+
+float
+my_scalbnf (float a, int b)
+{
+  return __builtin_scalbnf (a, b);
+}
+
+float
+my_ldexpf (float a, int b)
+{
+  return __builtin_ldexpf (a, b);
+}
+
+/* b must be sign-extended */
+double
+my_ldexp_long (double a, long b)
+{
+  return __builtin_ldexp (a, b);
+}
-- 
2.38.1

[PATCH 4/4] LoongArch: Add flogb.{s,d} instructions and expand logb{sf,df}2

[Xi Ruoyao]

On LoongArch, flogb instructions extract the exponent of a non-negative
floating point value, but produces NaN for negative values.  So we need
to add a fabs instruction when we expand logb.

gcc/ChangeLog:

	* config/loongarch/loongarch.md (UNSPEC_FLOGB): New unspec.
	(type): Add flogb.
	(logb_non_negative<mode>2): New instruction template.
	(logb<mode>2): New define_expand.

gcc/testsuite/ChangeLog:

	* gcc.target/loongarch/flogb.c: New test.
---
 gcc/config/loongarch/loongarch.md          | 35 ++++++++++++++++++++--
 gcc/testsuite/gcc.target/loongarch/flogb.c | 18 +++++++++++
 2 files changed, 51 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/loongarch/flogb.c

diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
index 9070ac4e2f8..072c3163b75 100644
--- a/gcc/config/loongarch/loongarch.md
+++ b/gcc/config/loongarch/loongarch.md
@@ -42,6 +42,7 @@ (define_c_enum "unspec" [
   UNSPEC_FTINTRM
   UNSPEC_FTINTRP
   UNSPEC_FSCALEB
+  UNSPEC_FLOGB
 
   ;; Override return address for exception handling.
   UNSPEC_EH_RETURN
@@ -217,6 +218,7 @@ (define_attr "qword_mode" "no,yes"
 ;; fdiv		floating point divide
 ;; frdiv	floating point reciprocal divide
 ;; fabs		floating point absolute value
+;; flogb	floating point exponent extract
 ;; fneg		floating point negation
 ;; fcmp		floating point compare
 ;; fcopysign	floating point copysign
@@ -233,8 +235,8 @@ (define_attr "type"
   "unknown,branch,jump,call,load,fpload,fpidxload,store,fpstore,fpidxstore,
    prefetch,prefetchx,condmove,mgtf,mftg,const,arith,logical,
    shift,slt,signext,clz,trap,imul,idiv,move,
-   fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,fneg,fcmp,fcopysign,fcvt,fscaleb,
-   fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost"
+   fmove,fadd,fmul,fmadd,fdiv,frdiv,fabs,flogb,fneg,fcmp,fcopysign,fcvt,
+   fscaleb,fsqrt,frsqrt,accext,accmod,multi,atomic,syncloop,nop,ghost"
   (cond [(eq_attr "jirl" "!unset") (const_string "call")
 	 (eq_attr "got" "load") (const_string "load")
 
@@ -1036,6 +1038,35 @@ (define_insn "ldexp<mode>3"
    (set_attr "mode" "<UNITMODE>")])
 \f
 ;;
+;;  ....................
+;;
+;;	FLOATING POINT EXPONENT EXTRACT
+;;
+;;  ....................
+
+(define_insn "logb_non_negative<mode>2"
+  [(set (match_operand:ANYF 0 "register_operand" "=f")
+	(unspec:ANYF [(match_operand:ANYF 1 "register_operand" "f")]
+		     UNSPEC_FLOGB))]
+  "TARGET_HARD_FLOAT"
+  "flogb.<fmt>\t%0,%1"
+  [(set_attr "type" "flogb")
+   (set_attr "mode" "<UNITMODE>")])
+
+(define_expand "logb<mode>2"
+  [(set (match_operand:ANYF 0 "register_operand")
+	(unspec:ANYF [(abs:ANYF (match_operand:ANYF 1 "register_operand"))]
+		     UNSPEC_FLOGB))]
+  "TARGET_HARD_FLOAT"
+{
+  rtx tmp = gen_reg_rtx (<MODE>mode);
+
+  emit_insn (gen_abs<mode>2 (tmp, operands[1]));
+  emit_insn (gen_logb_non_negative<mode>2 (operands[0], tmp));
+  DONE;
+})
+\f
+;;
 ;;  ...................
 ;;
 ;;  Count leading zeroes.
diff --git a/gcc/testsuite/gcc.target/loongarch/flogb.c b/gcc/testsuite/gcc.target/loongarch/flogb.c
new file mode 100644
index 00000000000..1daefe54e13
--- /dev/null
+++ b/gcc/testsuite/gcc.target/loongarch/flogb.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-mdouble-float -fno-math-errno" } */
+/* { dg-final { scan-assembler "fabs\\.s" } } */
+/* { dg-final { scan-assembler "fabs\\.d" } } */
+/* { dg-final { scan-assembler "flogb\\.s" } } */
+/* { dg-final { scan-assembler "flogb\\.d" } } */
+
+double
+my_logb (double a)
+{
+  return __builtin_logb (a);
+}
+
+float
+my_logbf (float a)
+{
+  return __builtin_logbf (a);
+}
-- 
2.38.1

Re: [PATCH 2/4] LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions

[Lulu Cheng]

There is a paragraph in the explanation information for the compile 
parameter '-fno-fp-int-builtin-inexact' in the gcc.pdf document:

     "Do not allow the built-in functions ceil, floor, round and trunc, 
and their　float and long double variants,

     to generate code that raises the “inexact”　floating-point exception 
for noninteger arguments.

     ISO C99 and C11 allow　these functions to raise the “inexact” 
exception, but ISO/IEC TS 18661-1:2014,

     the C bindings to IEEE 754-2008, as integrated into ISO C2X, does 
not allow　these functions to do so."

So I think the implementation of these functions needs to be confirmed 
again.

Or am I misinterpreting this description?:-[


在 2022/11/9 下午3:21, Xi Ruoyao 写道:
> This allows to optimize the following builtins if -fno-math-errno:
>
> - __builtin_lrint{,f}
> - __builtin_lfloor{,f}
> - __builtin_lceil{,f}
>
> Inspired by
> https://gcc.gnu.org/pipermail/gcc-patches/2022-November/605287.html.
>
> ANYFI is added so the compiler won't try ftint.l.s if -mfpu=32.  If we
> simply used GPR here an ICE would be triggered with __builtin_lrintf
> and -mfpu=32.
>
> Note that the .w.{s,d} variants are not tested because we don't support
> ILP32 for now.
>
> gcc/ChangeLog:
>
> 	* config/loongarch/loongarch.md (UNSPEC_FTINT): New unspec.
> 	(UNSPEC_FTINTRM): Likewise.
> 	(UNSPEC_FTINTRP): Likewise.
> 	(LRINT): New define_int_iterator.
> 	(lrint_pattern): New define_int_attr.
> 	(lrint_submenmonic): Likewise.
> 	(ANYFI): New define_mode_iterator.
> 	(lrint<ANYF><ANYFI>): New instruction template.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.target/loongarch/ftint.c: New test.
> ---
>   gcc/config/loongarch/loongarch.md          | 28 ++++++++++++++
>   gcc/testsuite/gcc.target/loongarch/ftint.c | 44 ++++++++++++++++++++++
>   2 files changed, 72 insertions(+)
>   create mode 100644 gcc/testsuite/gcc.target/loongarch/ftint.c
>
> diff --git a/gcc/config/loongarch/loongarch.md b/gcc/config/loongarch/loongarch.md
> index a14ab14ac24..35cef272060 100644
> --- a/gcc/config/loongarch/loongarch.md
> +++ b/gcc/config/loongarch/loongarch.md
> @@ -38,6 +38,9 @@ (define_c_enum "unspec" [
>     UNSPEC_FMAX
>     UNSPEC_FMIN
>     UNSPEC_FCOPYSIGN
> +  UNSPEC_FTINT
> +  UNSPEC_FTINTRM
> +  UNSPEC_FTINTRP
>   
>     ;; Override return address for exception handling.
>     UNSPEC_EH_RETURN
> @@ -374,6 +377,11 @@ (define_mode_iterator QHWD [QI HI SI (DI "TARGET_64BIT")])
>   (define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT")
>   			    (DF "TARGET_DOUBLE_FLOAT")])
>   
> +;; Iterator for fixed-point modes which can be hold by a hardware
> +;; floating-point register.
> +(define_mode_iterator ANYFI [(SI "TARGET_HARD_FLOAT")
> +			     (DI "TARGET_DOUBLE_FLOAT")])
> +
>   ;; A mode for which moves involving FPRs may need to be split.
>   (define_mode_iterator SPLITF
>     [(DF "!TARGET_64BIT && TARGET_DOUBLE_FLOAT")
> @@ -515,6 +523,16 @@ (define_code_attr fcond [(unordered "cun")
>   (define_code_attr sel [(eq "masknez") (ne "maskeqz")])
>   (define_code_attr selinv [(eq "maskeqz") (ne "masknez")])
>   
> +;; Iterator and attributes for floating-point to fixed-point conversion
> +;; instructions.
> +(define_int_iterator LRINT [UNSPEC_FTINT UNSPEC_FTINTRM UNSPEC_FTINTRP])
> +(define_int_attr lrint_pattern [(UNSPEC_FTINT "lrint")
> +				(UNSPEC_FTINTRM "lfloor")
> +				(UNSPEC_FTINTRP "lceil")])
> +(define_int_attr lrint_submenmonic [(UNSPEC_FTINT "")
> +				    (UNSPEC_FTINTRM "rm")
> +				    (UNSPEC_FTINTRP "rp")])
> +
>   ;;
>   ;;  ....................
>   ;;
> @@ -2022,6 +2040,16 @@ (define_insn "rint<mode>2"
>     [(set_attr "type" "fcvt")
>      (set_attr "mode" "<MODE>")])
>   
> +;; Convert floating-point numbers to integers
> +(define_insn "<lrint_pattern><ANYF:mode><ANYFI:mode>2"
> +  [(set (match_operand:ANYFI 0 "register_operand" "=f")
> +	(unspec:ANYFI [(match_operand:ANYF 1 "register_operand" "f")]
> +		      LRINT))]
> +  "TARGET_HARD_FLOAT"
> +  "ftint<lrint_submenmonic>.<ANYFI:ifmt>.<ANYF:fmt> %0,%1"
> +  [(set_attr "type" "fcvt")
> +   (set_attr "mode" "<ANYF:MODE>")])
> +
>   ;; Load the low word of operand 0 with operand 1.
>   (define_insn "load_low<mode>"
>     [(set (match_operand:SPLITF 0 "register_operand" "=f,f")
> diff --git a/gcc/testsuite/gcc.target/loongarch/ftint.c b/gcc/testsuite/gcc.target/loongarch/ftint.c
> new file mode 100644
> index 00000000000..9c3c3a8a756
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/loongarch/ftint.c
> @@ -0,0 +1,44 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mabi=lp64d -mdouble-float -fno-math-errno" } */
> +/* { dg-final { scan-assembler "ftint\\.l\\.s" } } */
> +/* { dg-final { scan-assembler "ftint\\.l\\.d" } } */
> +/* { dg-final { scan-assembler "ftintrm\\.l\\.s" } } */
> +/* { dg-final { scan-assembler "ftintrm\\.l\\.d" } } */
> +/* { dg-final { scan-assembler "ftintrp\\.l\\.s" } } */
> +/* { dg-final { scan-assembler "ftintrp\\.l\\.d" } } */
> +
> +long
> +my_lrint (double a)
> +{
> +  return __builtin_lrint (a);
> +}
> +
> +long
> +my_lrintf (float a)
> +{
> +  return __builtin_lrintf (a);
> +}
> +
> +long
> +my_lfloor (double a)
> +{
> +  return __builtin_lfloor (a);
> +}
> +
> +long
> +my_lfloorf (float a)
> +{
> +  return __builtin_lfloorf (a);
> +}
> +
> +long
> +my_lceil (double a)
> +{
> +  return __builtin_lceil (a);
> +}
> +
> +long
> +my_lceilf (float a)
> +{
> +  return __builtin_lceilf (a);
> +}

Re: [PATCH 2/4] LoongArch: Add ftint{,rm,rp}.{w,l}.{s,d} instructions

[Xi Ruoyao]

On Wed, 2022-11-09 at 15:46 +0800, Lulu Cheng wrote:
> There is a paragraph in the explanation information for the compile 
> parameter '-fno-fp-int-builtin-inexact' in the gcc.pdf document:
> 
>      "Do not allow the built-in functions ceil, floor, round and
> trunc, 
> and their　float and long double variants,
> 
>      to generate code that raises the “inexact”　floating-point
> exception 
> for noninteger arguments.
> 
>      ISO C99 and C11 allow　these functions to raise the “inexact” 
> exception, but ISO/IEC TS 18661-1:2014,
> 
>      the C bindings to IEEE 754-2008, as integrated into ISO C2X, does
> not allow　these functions to do so."
> 
> So I think the implementation of these functions needs to be confirmed
> again.
> 
> Or am I misinterpreting this description?:-[

You are correct, I'm wrong :(.

This patch breaks:

long x(double d)
{
	return __builtin_ceil(d);
}

The compiler then folds it into __builtin_lceil and produce
ftintrp.l.d $f0,$f0, even if -fno-fp-int-builtin-inexact is used.

I'll revise this patch to limit lceil and lfloor for -ffp-int-builtin-
inexact only.


-- 
Xi Ruoyao <xry111@xry111.site>
School of Aerospace Science and Technology, Xidian University