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* [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension
@ 2023-02-20  7:01 Liao Shihua
  2023-02-20  7:01 ` [PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
                   ` (5 more replies)
  0 siblings, 6 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-20  7:01 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Liao Shihua

This series adds basic support for the Scalar Cryptography extensions:
* Zbkb
* Zbkc
* Zbkx
* Zknd
* Zkne
* Zknh
* Zksed
* Zksh

The implementation follows the version Scalar Cryptography v1.0.0 of the specification,
which can be found here:
https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-scalar

It works by Wu Siyu and Liao Shihua .
Liao Shihua (5):
  Add prototypes for RISC-V Crypto built-in functions
  Implement ZBKB, ZBKC and ZBKX extensions
  Implement ZKND and ZKNE extensions
  Implement ZKNH extension
  Implement ZKSH and ZKSED extensions

 gcc/config/riscv/bitmanip.md                  |  20 +-
 gcc/config/riscv/constraints.md               |   8 +
 gcc/config/riscv/crypto.md                    | 435 ++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc            |  26 ++
 gcc/config/riscv/riscv-ftypes.def             |  10 +
 gcc/config/riscv/riscv-scalar-crypto.def      |  94 ++++
 gcc/config/riscv/riscv.md                     |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkb32.c       |  36 ++
 gcc/testsuite/gcc.target/riscv/zbkb64.c       |  28 ++
 gcc/testsuite/gcc.target/riscv/zbkc32.c       |  17 +
 gcc/testsuite/gcc.target/riscv/zbkc64.c       |  17 +
 gcc/testsuite/gcc.target/riscv/zbkx32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zbkx64.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zknd32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zknd64.c       |  36 ++
 gcc/testsuite/gcc.target/riscv/zkne32.c       |  18 +
 gcc/testsuite/gcc.target/riscv/zkne64.c       |  30 ++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  28 ++
 .../gcc.target/riscv/zknh-sha512-32.c         |  42 ++
 .../gcc.target/riscv/zknh-sha512-64.c         |  31 ++
 gcc/testsuite/gcc.target/riscv/zksed32.c      |  19 +
 gcc/testsuite/gcc.target/riscv/zksed64.c      |  19 +
 gcc/testsuite/gcc.target/riscv/zksh32.c       |  19 +
 gcc/testsuite/gcc.target/riscv/zksh64.c       |  19 +
 24 files changed, 999 insertions(+), 11 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-scalar-crypto.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions
  2023-02-20  7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
@ 2023-02-20  7:01 ` Liao Shihua
  2023-02-20  7:01 ` [PATCH V3 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Liao Shihua
                   ` (4 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-20  7:01 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Liao Shihua

This patch adds prototypes for RISC-V Crypto built-in functions.

gcc/ChangeLog:

        * config/riscv/riscv-builtins.cc (RISCV_FTYPE_NAME2):
        (RISCV_FTYPE_NAME3):
        (RISCV_ATYPE_QI):
        (RISCV_ATYPE_HI):
        (RISCV_FTYPE_ATYPES2):
        (RISCV_FTYPE_ATYPES3):
        * config/riscv/riscv-ftypes.def (2):
        (3):

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/riscv-builtins.cc |  8 ++++++++
 gcc/config/riscv/riscv-ftypes.def  | 10 ++++++++++
 2 files changed, 18 insertions(+)

diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 25ca407f9a9..ded91e17554 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -42,6 +42,8 @@ along with GCC; see the file COPYING3.  If not see
 /* Macros to create an enumeration identifier for a function prototype.  */
 #define RISCV_FTYPE_NAME0(A) RISCV_##A##_FTYPE
 #define RISCV_FTYPE_NAME1(A, B) RISCV_##A##_FTYPE_##B
+#define RISCV_FTYPE_NAME2(A, B, C) RISCV_##A##_FTYPE_##B##_##C
+#define RISCV_FTYPE_NAME3(A, B, C, D) RISCV_##A##_FTYPE_##B##_##C##_##D
 
 /* Classifies the prototype of a built-in function.  */
 enum riscv_function_type {
@@ -132,6 +134,8 @@ AVAIL (always,     (!0))
 /* Argument types.  */
 #define RISCV_ATYPE_VOID void_type_node
 #define RISCV_ATYPE_USI unsigned_intSI_type_node
+#define RISCV_ATYPE_QI intQI_type_node
+#define RISCV_ATYPE_HI intHI_type_node
 #define RISCV_ATYPE_SI intSI_type_node
 #define RISCV_ATYPE_DI intDI_type_node
 #define RISCV_ATYPE_VOID_PTR ptr_type_node
@@ -142,6 +146,10 @@ AVAIL (always,     (!0))
   RISCV_ATYPE_##A
 #define RISCV_FTYPE_ATYPES1(A, B) \
   RISCV_ATYPE_##A, RISCV_ATYPE_##B
+#define RISCV_FTYPE_ATYPES2(A, B, C) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C
+#define RISCV_FTYPE_ATYPES3(A, B, C, D) \
+  RISCV_ATYPE_##A, RISCV_ATYPE_##B, RISCV_ATYPE_##C, RISCV_ATYPE_##D
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
diff --git a/gcc/config/riscv/riscv-ftypes.def b/gcc/config/riscv/riscv-ftypes.def
index 3a40c33e7c2..3b518195a29 100644
--- a/gcc/config/riscv/riscv-ftypes.def
+++ b/gcc/config/riscv/riscv-ftypes.def
@@ -32,3 +32,13 @@ DEF_RISCV_FTYPE (1, (VOID, USI))
 DEF_RISCV_FTYPE (1, (VOID, VOID_PTR))
 DEF_RISCV_FTYPE (1, (SI, SI))
 DEF_RISCV_FTYPE (1, (DI, DI))
+DEF_RISCV_FTYPE (2, (SI, QI, QI))
+DEF_RISCV_FTYPE (2, (SI, HI, HI))
+DEF_RISCV_FTYPE (2, (SI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, QI, QI))
+DEF_RISCV_FTYPE (2, (DI, HI, HI))
+DEF_RISCV_FTYPE (2, (DI, SI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, SI))
+DEF_RISCV_FTYPE (2, (DI, DI, DI))
+DEF_RISCV_FTYPE (3, (SI, SI, SI, SI))
+DEF_RISCV_FTYPE (3, (DI, DI, DI, SI))
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH V3 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions
  2023-02-20  7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
  2023-02-20  7:01 ` [PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
@ 2023-02-20  7:01 ` Liao Shihua
  2023-02-20  7:01 ` [PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions Liao Shihua
                   ` (3 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-20  7:01 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Liao Shihua

This patch supports Zkbk, Zbkc and Zkbx extension. 
It includes instruction's machine description and built-in funtions. 
It is worth mentioning that this patch only adds instructions in Zbkb but no longer in Zbb.
If any instructions both in Zbb and Zbkb, they will be generated by code generator instead of built-in functions.

gcc/ChangeLog:

        * config/riscv/bitmanip.md: Add ZBKB's instructions.
        * config/riscv/riscv-builtins.cc (AVAIL): 
        * config/riscv/riscv.md:
        * config/riscv/crypto.md: Add Scalar Cryptography extension's machine description file.
        * config/riscv/riscv-scalar-crypto.def: Add Scalar Cryptography extension's built-in function file.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zbkb32.c: New test.
        * gcc.target/riscv/zbkb64.c: New test.
        * gcc.target/riscv/zbkc32.c: New test.
        * gcc.target/riscv/zbkc64.c: New test.
        * gcc.target/riscv/zbkx32.c: New test.
        * gcc.target/riscv/zbkx64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/bitmanip.md             |  20 ++--
 gcc/config/riscv/crypto.md               | 128 +++++++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc       |   7 ++
 gcc/config/riscv/riscv-scalar-crypto.def |  45 ++++++++
 gcc/config/riscv/riscv.md                |   4 +-
 gcc/testsuite/gcc.target/riscv/zbkb32.c  |  36 +++++++
 gcc/testsuite/gcc.target/riscv/zbkb64.c  |  28 +++++
 gcc/testsuite/gcc.target/riscv/zbkc32.c  |  17 +++
 gcc/testsuite/gcc.target/riscv/zbkc64.c  |  17 +++
 gcc/testsuite/gcc.target/riscv/zbkx32.c  |  18 ++++
 gcc/testsuite/gcc.target/riscv/zbkx64.c  |  18 ++++
 11 files changed, 327 insertions(+), 11 deletions(-)
 create mode 100644 gcc/config/riscv/crypto.md
 create mode 100644 gcc/config/riscv/riscv-scalar-crypto.def
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index 14d18edbe62..f076ba35832 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -189,7 +189,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
         (bitmanip_bitwise:X (not:X (match_operand:X 1 "register_operand" "r"))
                             (match_operand:X 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "<insn>n\t%0,%2,%1"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -203,7 +203,7 @@
 			       (const_int 0)))
 		(match_operand:DI 2 "register_operand")))
    (clobber (match_operand:DI 3 "register_operand"))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   [(set (match_dup 3) (ashiftrt:DI (match_dup 1) (const_int 63)))
    (set (match_dup 0) (and:DI (not:DI (match_dup 3)) (match_dup 2)))])
 
@@ -211,7 +211,7 @@
   [(set (match_operand:X 0 "register_operand" "=r")
         (not:X (xor:X (match_operand:X 1 "register_operand" "r")
                       (match_operand:X 2 "register_operand" "r"))))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "xnor\t%0,%1,%2"
   [(set_attr "type" "bitmanip")
    (set_attr "mode" "<X:MODE>")])
@@ -277,7 +277,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotatert:SI (match_operand:SI 1 "register_operand" "r")
 		     (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "ror%i2%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -285,7 +285,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(rotatert:DI (match_operand:DI 1 "register_operand" "r")
 		     (match_operand:QI 2 "arith_operand" "rI")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "ror%i2\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -293,7 +293,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (rotatert:SI (match_operand:SI 1 "register_operand" "r")
 				     (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rorw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -301,7 +301,7 @@
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(rotate:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rol%~\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -309,7 +309,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(rotate:DI (match_operand:DI 1 "register_operand" "r")
 		   (match_operand:QI 2 "register_operand" "r")))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rol\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -317,7 +317,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r")
 	(sign_extend:DI (rotate:SI (match_operand:SI 1 "register_operand" "r")
 				   (match_operand:QI 2 "register_operand" "r"))))]
-  "TARGET_64BIT && TARGET_ZBB"
+  "TARGET_64BIT && (TARGET_ZBB || TARGET_ZBKB)"
   "rolw\t%0,%1,%2"
   [(set_attr "type" "bitmanip")])
 
@@ -332,7 +332,7 @@
 (define_insn "bswap<mode>2"
   [(set (match_operand:X 0 "register_operand" "=r")
         (bswap:X (match_operand:X 1 "register_operand" "r")))]
-  "TARGET_ZBB"
+  "TARGET_ZBB || TARGET_ZBKB"
   "rev8\t%0,%1"
   [(set_attr "type" "bitmanip")])
 
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
new file mode 100644
index 00000000000..a270036e39b
--- /dev/null
+++ b/gcc/config/riscv/crypto.md
@@ -0,0 +1,128 @@
+;; Machine description for RISC-V Scalar Cryptography extensions.
+;; Copyright (C) 2023 Free Software Foundation, Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+(define_c_enum "unspec" [
+    ;; Zbkb unspecs
+    UNSPEC_BREV8
+    UNSPEC_ZIP
+    UNSPEC_UNZIP
+    UNSPEC_PACK
+    UNSPEC_PACKH
+    UNSPEC_PACKW
+
+    ;; Zbkc unspecs
+    UNSPEC_CLMUL
+    UNSPEC_CLMULH
+
+    ;; Zbkx unspecs
+    UNSPEC_XPERM8
+    UNSPEC_XPERM4
+])
+
+;; ZBKB extension
+(define_insn "riscv_brev8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_BREV8))]
+  "TARGET_ZBKB"
+  "brev8\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_zip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+                  UNSPEC_ZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "zip\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_unzip"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
+                  UNSPEC_UNZIP))]
+  "TARGET_ZBKB && !TARGET_64BIT"
+  "unzip\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_pack_<X:mode><HISI:mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:HISI 1 "register_operand" "r")
+                  (match_operand:HISI 2 "register_operand" "r")]
+                  UNSPEC_PACK))]
+  "TARGET_ZBKB"
+  "pack\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_packh_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:QI 1 "register_operand" "r")
+                  (match_operand:QI 2 "register_operand" "r")]
+                  UNSPEC_PACKH))]
+  "TARGET_ZBKB"
+  "packh\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_packw"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:HI 1 "register_operand" "r")
+                  (match_operand:HI 2 "register_operand" "r")]
+                  UNSPEC_PACKW))]
+  "TARGET_ZBKB && TARGET_64BIT"
+  "packw\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZBKC extension
+
+(define_insn "riscv_clmul_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_CLMUL))]
+  "TARGET_ZBKC"
+  "clmul\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_clmulh_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_CLMULH))]
+  "TARGET_ZBKC"
+  "clmulh\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZBKX extension
+
+(define_insn "riscv_xperm4_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM4))]
+  "TARGET_ZBKX"
+  "xperm4\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_xperm8_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")]
+                  UNSPEC_XPERM8))]
+  "TARGET_ZBKX"
+  "xperm8\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index ded91e17554..f0d60709c7d 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -100,6 +100,12 @@ AVAIL (zero32,  TARGET_ZICBOZ && !TARGET_64BIT)
 AVAIL (zero64,  TARGET_ZICBOZ && TARGET_64BIT)
 AVAIL (prefetchi32, TARGET_ZICBOP && !TARGET_64BIT)
 AVAIL (prefetchi64, TARGET_ZICBOP && TARGET_64BIT)
+AVAIL (crypto_zbkb32, TARGET_ZBKB && !TARGET_64BIT)
+AVAIL (crypto_zbkb64, TARGET_ZBKB && TARGET_64BIT)
+AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT)
+AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT)
+AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
+AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
@@ -153,6 +159,7 @@ AVAIL (always,     (!0))
 
 static const struct riscv_builtin_description riscv_builtins[] = {
   #include "riscv-cmo.def"
+  #include "riscv-scalar-crypto.def"
 
   DIRECT_BUILTIN (frflags, RISCV_USI_FTYPE, hard_float),
   DIRECT_NO_TARGET_BUILTIN (fsflags, RISCV_VOID_FTYPE_USI, hard_float),
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
new file mode 100644
index 00000000000..e4c97acbc05
--- /dev/null
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -0,0 +1,45 @@
+/* Builtin functions for RISC-V Scalar Cryptography extensions.
+   Copyright (C) 2023 Free Software Foundation, Inc.
+
+This file is part of GCC.
+
+GCC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 3, or (at your option)
+any later version.
+
+GCC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GCC; see the file COPYING3.  If not see
+<http://www.gnu.org/licenses/>.  */
+
+// ZBKB
+RISCV_BUILTIN (pack_sihi, "pack", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_HI_HI, crypto_zbkb32),
+RISCV_BUILTIN (pack_disi, "pack", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_SI_SI, crypto_zbkb64),
+
+RISCV_BUILTIN (packh_si, "packh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_QI_QI, crypto_zbkb32),
+RISCV_BUILTIN (packh_di, "packh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_QI_QI, crypto_zbkb64),
+
+RISCV_BUILTIN (packw, "packw", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_HI_HI, crypto_zbkb64),
+
+RISCV_BUILTIN (zip, "zip", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+RISCV_BUILTIN (unzip, "unzip", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+
+RISCV_BUILTIN (brev8_si, "brev8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zbkb32),
+RISCV_BUILTIN (brev8_di, "brev8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zbkb64),
+
+// ZBKC
+RISCV_BUILTIN (clmul_si, "clmul", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmul_di, "clmul", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+RISCV_BUILTIN (clmulh_si, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkc32),
+RISCV_BUILTIN (clmulh_di, "clmulh", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkc64),
+
+// ZBKX
+RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
+RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c8adc5af5d2..ddd014b1bb5 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -242,6 +242,7 @@
 ;; bitmanip	bit manipulation instructions
 ;; rotate   rotation instructions
 ;; atomic   atomic instructions
+;; crypto cryptography instructions
 ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
 ;; rdvlenb     vector byte length vlenb csrr read
 ;; rdvl        vector length vl csrr read
@@ -333,7 +334,7 @@
   "unknown,branch,jump,call,load,fpload,store,fpstore,
    mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
    fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate,
-   atomic,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
+   atomic,crypto,rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts,
    vldux,vldox,vstux,vstox,vldff,vldr,vstr,
    vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,
    vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,
@@ -3086,6 +3087,7 @@
 )
 
 (include "bitmanip.md")
+(include "crypto.md")
 (include "sync.md")
 (include "peephole.md")
 (include "pic.md")
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb32.c b/gcc/testsuite/gcc.target/riscv/zbkb32.c
new file mode 100644
index 00000000000..d12cec226ff
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb32.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkb -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int16_t rs1, int16_t rs2)
+{
+    return __builtin_riscv_pack(rs1, rs2);
+}
+
+int32_t foo2(int8_t rs1, int8_t rs2)
+{
+    return __builtin_riscv_packh(rs1, rs2);
+}
+
+int32_t foo3(int32_t rs1)
+{
+    return __builtin_riscv_brev8(rs1);
+}
+
+int32_t foo4(int32_t rs1)
+{
+    return __builtin_riscv_zip(rs1);
+}
+
+int32_t foo5(int32_t rs1)
+{
+    return __builtin_riscv_unzip(rs1);
+}
+
+/* { dg-final { scan-assembler-times "pack\t" 1 } } */
+/* { dg-final { scan-assembler-times "packh" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
+/* { dg-final { scan-assembler-times "\tzip\t" 1 } } */
+/* { dg-final { scan-assembler-times "unzip" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkb64.c b/gcc/testsuite/gcc.target/riscv/zbkb64.c
new file mode 100644
index 00000000000..645a35324c0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkb64.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkb -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include <stdint.h>
+
+int64_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_pack(rs1, rs2);
+}
+
+int64_t foo2(int8_t rs1, int8_t rs2)
+{
+    return __builtin_riscv_packh(rs1, rs2);
+}
+
+int64_t foo3(int16_t rs1, int16_t rs2)
+{
+    return __builtin_riscv_packw(rs1, rs2);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_brev8(rs1);
+}
+/* { dg-final { scan-assembler-times "pack\t" 1 } } */
+/* { dg-final { scan-assembler-times "packh" 1 } } */
+/* { dg-final { scan-assembler-times "packw" 1 } } */
+/* { dg-final { scan-assembler-times "brev8" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc32.c b/gcc/testsuite/gcc.target/riscv/zbkc32.c
new file mode 100644
index 00000000000..aae588e6933
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc32.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkc -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_clmul(rs1, rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_clmulh(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkc64.c b/gcc/testsuite/gcc.target/riscv/zbkc64.c
new file mode 100644
index 00000000000..3cb9ff711f2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkc64.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkc -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_clmul(rs1, rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_clmulh(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "clmul\t" 1 } } */
+/* { dg-final { scan-assembler-times "clmulh" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx32.c b/gcc/testsuite/gcc.target/riscv/zbkx32.c
new file mode 100644
index 00000000000..dc3161bc494
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkx32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zbkx -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo3(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_xperm8(rs1, rs2);
+}
+
+int32_t foo4(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_xperm4(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zbkx64.c b/gcc/testsuite/gcc.target/riscv/zbkx64.c
new file mode 100644
index 00000000000..dbf3407cca4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbkx64.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zbkx -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_xperm8(rs1, rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_xperm4(rs1, rs2);
+}
+
+/* { dg-final { scan-assembler-times "xperm8" 1 } } */
+/* { dg-final { scan-assembler-times "xperm4" 1 } } */
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions
  2023-02-20  7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
  2023-02-20  7:01 ` [PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
  2023-02-20  7:01 ` [PATCH V3 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Liao Shihua
@ 2023-02-20  7:01 ` Liao Shihua
  2023-02-20  7:01 ` [PATCH V3 4/5] RISC-V: Implement ZKNH extension Liao Shihua
                   ` (2 subsequent siblings)
  5 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-20  7:01 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Liao Shihua

This patch supports Zkne and Zknd extension. 
It includes instruction's machine description and built-in funtions. 

gcc/ChangeLog:

        * config/riscv/constraints.md (D03): Add constants of bs and rnum.
        (DsA):
        * config/riscv/crypto.md (riscv_aes32dsi): Add ZKND's and ZKNE's instructions.
        (riscv_aes32dsmi):
        (riscv_aes64ds):
        (riscv_aes64dsm):
        (riscv_aes64im):
        (riscv_aes64ks1i):
        (riscv_aes64ks2):
        (riscv_aes32esi):
        (riscv_aes32esmi):
        (riscv_aes64es):
        (riscv_aes64esm):
        * config/riscv/riscv-builtins.cc (AVAIL): Add ZKND's and ZKNE's AVAIL.
        * config/riscv/riscv-scalar-crypto.def (DIRECT_BUILTIN): Add ZKND's and ZKNE's built-in functions.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zknd32.c: New test.
        * gcc.target/riscv/zknd64.c: New test.
        * gcc.target/riscv/zkne32.c: New test.
        * gcc.target/riscv/zkne64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/constraints.md          |   8 ++
 gcc/config/riscv/crypto.md               | 121 +++++++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc       |   5 +
 gcc/config/riscv/riscv-scalar-crypto.def |  15 +++
 gcc/testsuite/gcc.target/riscv/zknd32.c  |  18 ++++
 gcc/testsuite/gcc.target/riscv/zknd64.c  |  36 +++++++
 gcc/testsuite/gcc.target/riscv/zkne32.c  |  18 ++++
 gcc/testsuite/gcc.target/riscv/zkne64.c  |  30 ++++++
 8 files changed, 251 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index 3637380ee47..3f46f14b10f 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -83,6 +83,14 @@
   (and (match_code "const_int")
        (match_test "SINGLE_BIT_MASK_OPERAND (~ival)")))
 
+(define_constraint "D03"
+  "0, 1, 2 or 3 immediate"
+  (match_test "IN_RANGE (ival, 0, 3)"))
+
+(define_constraint "DsA"
+  "0 - 10 immediate"
+  (match_test "IN_RANGE (ival, 0, 10)"))
+
 ;; Floating-point constant +0.0, used for FCVT-based moves when FMV is
 ;; not available in RV32.
 (define_constraint "G"
diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index a270036e39b..7568466ec97 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -33,6 +33,21 @@
     ;; Zbkx unspecs
     UNSPEC_XPERM8
     UNSPEC_XPERM4
+
+    ;; Zknd unspecs
+    UNSPEC_AES_DSI
+    UNSPEC_AES_DSMI
+    UNSPEC_AES_DS
+    UNSPEC_AES_DSM
+    UNSPEC_AES_IM
+    UNSPEC_AES_KS1I
+    UNSPEC_AES_KS2
+
+    ;; Zkne unspecs
+    UNSPEC_AES_ES
+    UNSPEC_AES_ESM
+    UNSPEC_AES_ESI
+    UNSPEC_AES_ESMI
 ])
 
 ;; ZBKB extension
@@ -126,3 +141,109 @@
   "TARGET_ZBKX"
   "xperm8\t%0,%1,%2"
   [(set_attr "type" "crypto")])
+
+;; ZKND extension
+
+(define_insn "riscv_aes32dsi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "register_operand" "D03")]
+                   UNSPEC_AES_DSI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32dsmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "register_operand" "D03")]
+                   UNSPEC_AES_DSMI))]
+  "TARGET_ZKND && !TARGET_64BIT"
+  "aes32dsmi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ds"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_DS))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64ds\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64dsm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_DSM))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64dsm\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64im"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_AES_IM))]
+  "TARGET_ZKND && TARGET_64BIT"
+  "aes64im\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ks1i"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "DsA")]
+                   UNSPEC_AES_KS1I))]
+  "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
+  "aes64ks1i\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64ks2"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_KS2))]
+  "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT"
+  "aes64ks2\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+;; ZKNE extension
+
+(define_insn "riscv_aes32esi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "register_operand" "D03")]
+                   UNSPEC_AES_ESI))]
+  "TARGET_ZKNE && !TARGET_64BIT"
+  "aes32esi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes32esmi"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")
+                   (match_operand:SI 3 "register_operand" "D03")]
+                   UNSPEC_AES_ESMI))]
+  "TARGET_ZKNE && !TARGET_64BIT"
+  "aes32esmi\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64es"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_ES))]
+  "TARGET_ZKNE && TARGET_64BIT"
+  "aes64es\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_aes64esm"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")
+                   (match_operand:DI 2 "register_operand" "r")]
+                   UNSPEC_AES_ESM))]
+  "TARGET_ZKNE && TARGET_64BIT"
+  "aes64esm\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index f0d60709c7d..6632009734b 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -106,6 +106,11 @@ AVAIL (crypto_zbkc32, TARGET_ZBKC && !TARGET_64BIT)
 AVAIL (crypto_zbkc64, TARGET_ZBKC && TARGET_64BIT)
 AVAIL (crypto_zbkx32, TARGET_ZBKX && !TARGET_64BIT)
 AVAIL (crypto_zbkx64, TARGET_ZBKX && TARGET_64BIT)
+AVAIL (crypto_zknd32, TARGET_ZKND && !TARGET_64BIT)
+AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
+AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
+AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
+AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
index e4c97acbc05..fe1a4e13d2d 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -43,3 +43,18 @@ RISCV_BUILTIN (xperm4_si, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI,
 RISCV_BUILTIN (xperm4_di, "xperm4", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
 RISCV_BUILTIN (xperm8_si, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI, crypto_zbkx32),
 RISCV_BUILTIN (xperm8_di, "xperm8", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI, crypto_zbkx64),
+
+// ZKND
+DIRECT_BUILTIN (aes32dsi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes32dsmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zknd32),
+DIRECT_BUILTIN (aes64ds, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64dsm, RISCV_DI_FTYPE_DI_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64im, RISCV_DI_FTYPE_DI, crypto_zknd64),
+DIRECT_BUILTIN (aes64ks1i, RISCV_DI_FTYPE_DI_SI, crypto_zkne_or_zknd),
+DIRECT_BUILTIN (aes64ks2, RISCV_DI_FTYPE_DI_DI, crypto_zkne_or_zknd),
+
+// ZKNE
+DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
+DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
diff --git a/gcc/testsuite/gcc.target/riscv/zknd32.c b/gcc/testsuite/gcc.target/riscv/zknd32.c
new file mode 100644
index 00000000000..203e3337d2a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknd32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zknd -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2, int bs)
+{
+    return __builtin_riscv_aes32dsi(rs1,rs2,bs);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2, int bs)
+{
+    return __builtin_riscv_aes32dsmi(rs1,rs2,bs);
+}
+
+/* { dg-final { scan-assembler-times "aes32dsi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32dsmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknd64.c b/gcc/testsuite/gcc.target/riscv/zknd64.c
new file mode 100644
index 00000000000..396c512fd3b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknd64.c
@@ -0,0 +1,36 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknd -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_aes64ds(rs1,rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_aes64dsm(rs1,rs2);
+}
+
+int64_t foo3(int64_t rs1, int rnum)
+{
+    return __builtin_riscv_aes64ks1i(rs1,rnum);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_aes64ks2(rs1,rs2);
+}
+
+int64_t foo5(int64_t rs1)
+{
+    return __builtin_riscv_aes64im(rs1);
+}
+
+/* { dg-final { scan-assembler-times "aes64ds\t" 1 } } */
+/* { dg-final { scan-assembler-times "aes64dsm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
+/* { dg-final { scan-assembler-times "aes64im" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zkne32.c b/gcc/testsuite/gcc.target/riscv/zkne32.c
new file mode 100644
index 00000000000..b3bf984a140
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zkne32.c
@@ -0,0 +1,18 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zkne -mabi=ilp32d" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2, int bs)
+{
+    return __builtin_riscv_aes32esi(rs1, rs2, bs);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2, int bs)
+{
+    return __builtin_riscv_aes32esmi(rs1, rs2, bs);
+}
+
+/* { dg-final { scan-assembler-times "aes32esi" 1 } } */
+/* { dg-final { scan-assembler-times "aes32esmi" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zkne64.c b/gcc/testsuite/gcc.target/riscv/zkne64.c
new file mode 100644
index 00000000000..894bab44fb0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zkne64.c
@@ -0,0 +1,30 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zkne -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_aes64es(rs1,rs2);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_aes64esm(rs1,rs2);
+}
+
+int64_t foo3(int64_t rs1, int rnum)
+{
+    return __builtin_riscv_aes64ks1i(rs1,rnum);
+}
+
+int64_t foo4(int64_t rs1, int64_t rs2)
+{
+    return __builtin_riscv_aes64ks2(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "aes64es\t" 1 } } */
+/* { dg-final { scan-assembler-times "aes64esm" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks1i" 1 } } */
+/* { dg-final { scan-assembler-times "aes64ks2" 1 } } */
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH V3 4/5] RISC-V: Implement ZKNH extension
  2023-02-20  7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
                   ` (2 preceding siblings ...)
  2023-02-20  7:01 ` [PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions Liao Shihua
@ 2023-02-20  7:01 ` Liao Shihua
  2023-02-20  7:01 ` [PATCH V3 5/5] RISC-V: Implement ZKSH and ZKSED extensions Liao Shihua
  2023-03-05 10:19 ` [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Kito Cheng
  5 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-20  7:01 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Liao Shihua

This patch supports Zknh extension. 
It includes instruction's machine description and built-in funtions. 

gcc/ChangeLog:

        * config/riscv/crypto.md (riscv_sha256sig0_<mode>): Add ZKNH's instructions.
        (riscv_sha256sig1_<mode>):
        (riscv_sha256sum0_<mode>):
        (riscv_sha256sum1_<mode>):
        (riscv_sha512sig0h):
        (riscv_sha512sig0l):
        (riscv_sha512sig1h):
        (riscv_sha512sig1l):
        (riscv_sha512sum0r):
        (riscv_sha512sum1r):
        (riscv_sha512sig0):
        (riscv_sha512sig1):
        (riscv_sha512sum0):
        (riscv_sha512sum1):
        * config/riscv/riscv-builtins.cc (AVAIL): And ZKNH's AVAIL.
        * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): And ZKNH's built-in functions.
        (DIRECT_BUILTIN):

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zknh-sha256.c: New test.
        * gcc.target/riscv/zknh-sha512-32.c: New test.
        * gcc.target/riscv/zknh-sha512-64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md                    | 138 ++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc            |   2 +
 gcc/config/riscv/riscv-scalar-crypto.def      |  22 +++
 gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  28 ++++
 .../gcc.target/riscv/zknh-sha512-32.c         |  42 ++++++
 .../gcc.target/riscv/zknh-sha512-64.c         |  31 ++++
 6 files changed, 263 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 7568466ec97..17e7440c0b5 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -48,6 +48,22 @@
     UNSPEC_AES_ESM
     UNSPEC_AES_ESI
     UNSPEC_AES_ESMI
+
+    ;; Zknh unspecs
+    UNSPEC_SHA_256_SIG0
+    UNSPEC_SHA_256_SIG1
+    UNSPEC_SHA_256_SUM0
+    UNSPEC_SHA_256_SUM1
+    UNSPEC_SHA_512_SIG0
+    UNSPEC_SHA_512_SIG0H
+    UNSPEC_SHA_512_SIG0L
+    UNSPEC_SHA_512_SIG1
+    UNSPEC_SHA_512_SIG1H
+    UNSPEC_SHA_512_SIG1L
+    UNSPEC_SHA_512_SUM0
+    UNSPEC_SHA_512_SUM0R
+    UNSPEC_SHA_512_SUM1
+    UNSPEC_SHA_512_SUM1R
 ])
 
 ;; ZBKB extension
@@ -247,3 +263,125 @@
   "TARGET_ZKNE && TARGET_64BIT"
   "aes64esm\t%0,%1,%2"
   [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA256
+
+(define_insn "riscv_sha256sig0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SIG0))]
+  "TARGET_ZKNH"
+  "sha256sig0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sig1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SIG1))]
+  "TARGET_ZKNH"
+  "sha256sig1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SUM0))]
+  "TARGET_ZKNH"
+  "sha256sum0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha256sum1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SHA_256_SUM1))]
+  "TARGET_ZKNH"
+  "sha256sum1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKNH - SHA512
+
+(define_insn "riscv_sha512sig0h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig0l\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1h"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1H))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1h\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1l"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1L))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sig1l\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM0R))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sum0r\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum1r"
+  [(set (match_operand:SI 0 "register_operand" "=r")
+        (unspec:SI [(match_operand:SI 1 "register_operand" "r")
+                   (match_operand:SI 2 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM1R))]
+  "TARGET_ZKNH && !TARGET_64BIT"
+  "sha512sum1r\t%0,%1,%2"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG0))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sig0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sig1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SIG1))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sig1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum0"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM0))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sum0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sha512sum1"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+        (unspec:DI [(match_operand:DI 1 "register_operand" "r")]
+                   UNSPEC_SHA_512_SUM1))]
+  "TARGET_ZKNH && TARGET_64BIT"
+  "sha512sum1\t%0,%1"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index 6632009734b..ab5bd52ee7f 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -111,6 +111,8 @@ AVAIL (crypto_zknd64, TARGET_ZKND && TARGET_64BIT)
 AVAIL (crypto_zkne32, TARGET_ZKNE && !TARGET_64BIT)
 AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
+AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
+AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
index fe1a4e13d2d..d38aad122e5 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -58,3 +58,25 @@ DIRECT_BUILTIN (aes32esi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
 DIRECT_BUILTIN (aes32esmi, RISCV_SI_FTYPE_SI_SI_SI, crypto_zkne32),
 DIRECT_BUILTIN (aes64es, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
 DIRECT_BUILTIN (aes64esm, RISCV_DI_FTYPE_DI_DI, crypto_zkne64),
+
+// ZKNH
+RISCV_BUILTIN (sha256sig0_si, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig0_di, "sha256sig0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sig1_si, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sig1_di, "sha256sig1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum0_si, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum0_di, "sha256sum0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+RISCV_BUILTIN (sha256sum1_si, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zknh32),
+RISCV_BUILTIN (sha256sum1_di, "sha256sum1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+DIRECT_BUILTIN (sha512sig0h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig0l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1h, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sig1l, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum0r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+DIRECT_BUILTIN (sha512sum1r, RISCV_SI_FTYPE_SI_SI, crypto_zknh32),
+
+DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
+DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha256.c b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
new file mode 100644
index 00000000000..54329aa6af2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha256.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+long foo1(long rs1)
+{
+    return __builtin_riscv_sha256sig0(rs1);
+}
+
+long foo2(long rs1)
+{
+    return __builtin_riscv_sha256sig1(rs1);
+}
+
+long foo3(long rs1)
+{
+    return __builtin_riscv_sha256sum0(rs1);
+}
+
+long foo4(long rs1)
+{
+    return __builtin_riscv_sha256sum1(rs1);
+}
+
+/* { dg-final { scan-assembler-times "sha256sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha256sum1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
new file mode 100644
index 00000000000..eff9978922e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
@@ -0,0 +1,42 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zknh -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_sha512sig0h(rs1,rs2);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_sha512sig0l(rs1,rs2);
+}
+
+int32_t foo3(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_sha512sig1h(rs1,rs2);
+}
+
+int32_t foo4(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_sha512sig1l(rs1,rs2);
+}
+
+int32_t foo5(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_sha512sum0r(rs1,rs2);
+}
+
+int32_t foo6(int32_t rs1, int32_t rs2)
+{
+    return __builtin_riscv_sha512sum1r(rs1,rs2);
+}
+
+/* { dg-final { scan-assembler-times "sha512sig0h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig0l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1h" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1l" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0r" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1r" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
new file mode 100644
index 00000000000..53cbd302b3c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zknh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1)
+{
+    return __builtin_riscv_sha512sig0(rs1);
+}
+
+int64_t foo2(int64_t rs1)
+{
+    return __builtin_riscv_sha512sig1(rs1);
+}
+
+int64_t foo3(int64_t rs1)
+{
+    return __builtin_riscv_sha512sum0(rs1);
+}
+
+int64_t foo4(int64_t rs1)
+{
+    return __builtin_riscv_sha512sum1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sha512sig0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sig1" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum0" 1 } } */
+/* { dg-final { scan-assembler-times "sha512sum1" 1 } } */
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* [PATCH V3 5/5] RISC-V: Implement ZKSH and ZKSED extensions
  2023-02-20  7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
                   ` (3 preceding siblings ...)
  2023-02-20  7:01 ` [PATCH V3 4/5] RISC-V: Implement ZKNH extension Liao Shihua
@ 2023-02-20  7:01 ` Liao Shihua
  2023-03-05 10:19 ` [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Kito Cheng
  5 siblings, 0 replies; 7+ messages in thread
From: Liao Shihua @ 2023-02-20  7:01 UTC (permalink / raw)
  To: gcc-patches; +Cc: kito.cheng, Liao Shihua

This patch supports Zksh and Zksed extension. 
It includes instruction's machine description and built-in funtions. 

gcc/ChangeLog:

        * config/riscv/crypto.md (riscv_sm3p0_<mode>): Add ZKSED's and ZKSH's instructions.
        (riscv_sm3p1_<mode>):
        (riscv_sm4ed_<mode>):
        (riscv_sm4ks_<mode>):
        * config/riscv/riscv-builtins.cc (AVAIL): Add ZKSED's and ZKSH's AVAIL.
        * config/riscv/riscv-scalar-crypto.def (RISCV_BUILTIN): Add ZKSED's and ZKSH's built-in functions.

gcc/testsuite/ChangeLog:

        * gcc.target/riscv/zksed32.c: New test.
        * gcc.target/riscv/zksed64.c: New test.
        * gcc.target/riscv/zksh32.c: New test.
        * gcc.target/riscv/zksh64.c: New test.

Co-Authored-By: SiYu Wu
---
 gcc/config/riscv/crypto.md               | 48 ++++++++++++++++++++++++
 gcc/config/riscv/riscv-builtins.cc       |  4 ++
 gcc/config/riscv/riscv-scalar-crypto.def | 12 ++++++
 gcc/testsuite/gcc.target/riscv/zksed32.c | 19 ++++++++++
 gcc/testsuite/gcc.target/riscv/zksed64.c | 19 ++++++++++
 gcc/testsuite/gcc.target/riscv/zksh32.c  | 19 ++++++++++
 gcc/testsuite/gcc.target/riscv/zksh64.c  | 19 ++++++++++
 7 files changed, 140 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksed64.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
 create mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c

diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md
index 17e7440c0b5..777aa529005 100644
--- a/gcc/config/riscv/crypto.md
+++ b/gcc/config/riscv/crypto.md
@@ -64,6 +64,14 @@
     UNSPEC_SHA_512_SUM0R
     UNSPEC_SHA_512_SUM1
     UNSPEC_SHA_512_SUM1R
+
+    ;; Zksh unspecs
+    UNSPEC_SM3_P0
+    UNSPEC_SM3_P1
+
+    ;; Zksed unspecs
+    UNSPEC_SM4_ED
+    UNSPEC_SM4_KS
 ])
 
 ;; ZBKB extension
@@ -385,3 +393,43 @@
   "TARGET_ZKNH && TARGET_64BIT"
   "sha512sum1\t%0,%1"
   [(set_attr "type" "crypto")])
+
+ ;; ZKSH
+
+(define_insn "riscv_sm3p0_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P0))]
+  "TARGET_ZKSH"
+  "sm3p0\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm3p1_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")]
+                  UNSPEC_SM3_P1))]
+  "TARGET_ZKSH"
+  "sm3p1\t%0,%1"
+  [(set_attr "type" "crypto")])
+
+;; ZKSED
+
+(define_insn "riscv_sm4ed_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")
+                  (match_operand:SI 3 "register_operand" "D03")]
+                  UNSPEC_SM4_ED))]
+  "TARGET_ZKSED"
+  "sm4ed\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
+
+(define_insn "riscv_sm4ks_<mode>"
+  [(set (match_operand:X 0 "register_operand" "=r")
+        (unspec:X [(match_operand:X 1 "register_operand" "r")
+                  (match_operand:X 2 "register_operand" "r")
+                  (match_operand:SI 3 "register_operand" "D03")]
+                  UNSPEC_SM4_KS))]
+  "TARGET_ZKSED"
+  "sm4ks\t%0,%1,%2,%3"
+  [(set_attr "type" "crypto")])
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
index ab5bd52ee7f..390f8a38309 100644
--- a/gcc/config/riscv/riscv-builtins.cc
+++ b/gcc/config/riscv/riscv-builtins.cc
@@ -113,6 +113,10 @@ AVAIL (crypto_zkne64, TARGET_ZKNE && TARGET_64BIT)
 AVAIL (crypto_zkne_or_zknd, (TARGET_ZKNE || TARGET_ZKND) && TARGET_64BIT)
 AVAIL (crypto_zknh32, TARGET_ZKNH && !TARGET_64BIT)
 AVAIL (crypto_zknh64, TARGET_ZKNH && TARGET_64BIT)
+AVAIL (crypto_zksh32, TARGET_ZKSH && !TARGET_64BIT)
+AVAIL (crypto_zksh64, TARGET_ZKSH && TARGET_64BIT)
+AVAIL (crypto_zksed32, TARGET_ZKSED && !TARGET_64BIT)
+AVAIL (crypto_zksed64, TARGET_ZKSED && TARGET_64BIT)
 AVAIL (always,     (!0))
 
 /* Construct a riscv_builtin_description from the given arguments.
diff --git a/gcc/config/riscv/riscv-scalar-crypto.def b/gcc/config/riscv/riscv-scalar-crypto.def
index d38aad122e5..139793c6360 100644
--- a/gcc/config/riscv/riscv-scalar-crypto.def
+++ b/gcc/config/riscv/riscv-scalar-crypto.def
@@ -80,3 +80,15 @@ DIRECT_BUILTIN (sha512sig0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sig1, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum0, RISCV_DI_FTYPE_DI, crypto_zknh64),
 DIRECT_BUILTIN (sha512sum1, RISCV_DI_FTYPE_DI, crypto_zknh64),
+
+// ZKSH
+RISCV_BUILTIN (sm3p0_si, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p0_di, "sm3p0", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+RISCV_BUILTIN (sm3p1_si, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI, crypto_zksh32),
+RISCV_BUILTIN (sm3p1_di, "sm3p1", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI, crypto_zksh64),
+
+// ZKSED
+RISCV_BUILTIN (sm4ed_si, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ed_di, "sm4ed", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64),
+RISCV_BUILTIN (sm4ks_si, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_SI_FTYPE_SI_SI_SI, crypto_zksed32),
+RISCV_BUILTIN (sm4ks_di, "sm4ks", RISCV_BUILTIN_DIRECT, RISCV_DI_FTYPE_DI_DI_SI, crypto_zksed64),
diff --git a/gcc/testsuite/gcc.target/riscv/zksed32.c b/gcc/testsuite/gcc.target/riscv/zksed32.c
new file mode 100644
index 00000000000..38c7ef5a62b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksed32.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zksed -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1, int32_t rs2, int bs)
+{
+    return __builtin_riscv_sm4ks(rs1,rs2,bs);
+}
+
+int32_t foo2(int32_t rs1, int32_t rs2, int bs)
+{
+    return __builtin_riscv_sm4ed(rs1,rs2,bs);
+}
+
+
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksed64.c b/gcc/testsuite/gcc.target/riscv/zksed64.c
new file mode 100644
index 00000000000..323d4fe1070
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksed64.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zksed -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1, int64_t rs2, int bs)
+{
+    return __builtin_riscv_sm4ks(rs1,rs2,bs);
+}
+
+int64_t foo2(int64_t rs1, int64_t rs2, int bs)
+{
+    return __builtin_riscv_sm4ed(rs1,rs2,bs);
+}
+
+
+/* { dg-final { scan-assembler-times "sm4ks" 1 } } */
+/* { dg-final { scan-assembler-times "sm4ed" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksh32.c b/gcc/testsuite/gcc.target/riscv/zksh32.c
new file mode 100644
index 00000000000..edbabd8cdb7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksh32.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv32gc_zksh -mabi=ilp32" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int32_t foo1(int32_t rs1)
+{
+    return __builtin_riscv_sm3p0(rs1);
+}
+
+int32_t foo2(int32_t rs1)
+{
+    return __builtin_riscv_sm3p1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/zksh64.c b/gcc/testsuite/gcc.target/riscv/zksh64.c
new file mode 100644
index 00000000000..832a9557880
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zksh64.c
@@ -0,0 +1,19 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=rv64gc_zksh -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-g" "-flto"} } */
+
+#include <stdint.h>
+
+int64_t foo1(int64_t rs1)
+{
+    return __builtin_riscv_sm3p0(rs1);
+}
+
+int64_t foo2(int64_t rs1)
+{
+    return __builtin_riscv_sm3p1(rs1);
+}
+
+
+/* { dg-final { scan-assembler-times "sm3p0" 1 } } */
+/* { dg-final { scan-assembler-times "sm3p1" 1 } } */
-- 
2.38.1.windows.1


^ permalink raw reply	[flat|nested] 7+ messages in thread
* Re: [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension
  2023-02-20  7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
                   ` (4 preceding siblings ...)
  2023-02-20  7:01 ` [PATCH V3 5/5] RISC-V: Implement ZKSH and ZKSED extensions Liao Shihua
@ 2023-03-05 10:19 ` Kito Cheng
  5 siblings, 0 replies; 7+ messages in thread
From: Kito Cheng @ 2023-03-05 10:19 UTC (permalink / raw)
  To: Liao Shihua; +Cc: gcc-patches

Committed, thanks!

On Mon, Feb 20, 2023 at 3:01 PM Liao Shihua <shihua@iscas.ac.cn> wrote:
>
> This series adds basic support for the Scalar Cryptography extensions:
> * Zbkb
> * Zbkc
> * Zbkx
> * Zknd
> * Zkne
> * Zknh
> * Zksed
> * Zksh
>
> The implementation follows the version Scalar Cryptography v1.0.0 of the specification,
> which can be found here:
> https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0-scalar
>
> It works by Wu Siyu and Liao Shihua .
> Liao Shihua (5):
>   Add prototypes for RISC-V Crypto built-in functions
>   Implement ZBKB, ZBKC and ZBKX extensions
>   Implement ZKND and ZKNE extensions
>   Implement ZKNH extension
>   Implement ZKSH and ZKSED extensions
>
>  gcc/config/riscv/bitmanip.md                  |  20 +-
>  gcc/config/riscv/constraints.md               |   8 +
>  gcc/config/riscv/crypto.md                    | 435 ++++++++++++++++++
>  gcc/config/riscv/riscv-builtins.cc            |  26 ++
>  gcc/config/riscv/riscv-ftypes.def             |  10 +
>  gcc/config/riscv/riscv-scalar-crypto.def      |  94 ++++
>  gcc/config/riscv/riscv.md                     |   4 +-
>  gcc/testsuite/gcc.target/riscv/zbkb32.c       |  36 ++
>  gcc/testsuite/gcc.target/riscv/zbkb64.c       |  28 ++
>  gcc/testsuite/gcc.target/riscv/zbkc32.c       |  17 +
>  gcc/testsuite/gcc.target/riscv/zbkc64.c       |  17 +
>  gcc/testsuite/gcc.target/riscv/zbkx32.c       |  18 +
>  gcc/testsuite/gcc.target/riscv/zbkx64.c       |  18 +
>  gcc/testsuite/gcc.target/riscv/zknd32.c       |  18 +
>  gcc/testsuite/gcc.target/riscv/zknd64.c       |  36 ++
>  gcc/testsuite/gcc.target/riscv/zkne32.c       |  18 +
>  gcc/testsuite/gcc.target/riscv/zkne64.c       |  30 ++
>  gcc/testsuite/gcc.target/riscv/zknh-sha256.c  |  28 ++
>  .../gcc.target/riscv/zknh-sha512-32.c         |  42 ++
>  .../gcc.target/riscv/zknh-sha512-64.c         |  31 ++
>  gcc/testsuite/gcc.target/riscv/zksed32.c      |  19 +
>  gcc/testsuite/gcc.target/riscv/zksed64.c      |  19 +
>  gcc/testsuite/gcc.target/riscv/zksh32.c       |  19 +
>  gcc/testsuite/gcc.target/riscv/zksh64.c       |  19 +
>  24 files changed, 999 insertions(+), 11 deletions(-)
>  create mode 100644 gcc/config/riscv/crypto.md
>  create mode 100644 gcc/config/riscv/riscv-scalar-crypto.def
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbkb64.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbkc64.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zbkx64.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zknd32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zknd64.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zkne32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zkne64.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha256.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zknh-sha512-64.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zksed32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zksed64.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zksh32.c
>  create mode 100644 gcc/testsuite/gcc.target/riscv/zksh64.c
>
> --
> 2.38.1.windows.1
>

^ permalink raw reply	[flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-03-05 10:19 UTC | newest]

Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-02-20  7:01 [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Liao Shihua
2023-02-20  7:01 ` [PATCH V3 1/5] RISC-V: Add prototypes for RISC-V Crypto built-in functions Liao Shihua
2023-02-20  7:01 ` [PATCH V3 2/5] RISC-V: Implement ZBKB, ZBKC and ZBKX extensions Liao Shihua
2023-02-20  7:01 ` [PATCH V3 3/5] RISC-V: Implement ZKND and ZKNE extensions Liao Shihua
2023-02-20  7:01 ` [PATCH V3 4/5] RISC-V: Implement ZKNH extension Liao Shihua
2023-02-20  7:01 ` [PATCH V3 5/5] RISC-V: Implement ZKSH and ZKSED extensions Liao Shihua
2023-03-05 10:19 ` [PATCH V3 0/5] RISC-V: Implement Scalar Cryptography Extension Kito Cheng

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