[PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations

[Michael Collison <collison@rivosinc.com>]

2023-03-02  Michael Collison  <collison@rivosinc.com>
	    Juzhe Zhong  <juzhe.zhong@rivai.ai>

	* config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include
	vector-iterators.md.
	* config/riscv/vector-auto.md: New file containing
	autovectorization patterns.
	* config/riscv/vector-iterators.md (UNSPEC_VADD/UNSPEC_VSUB):
	New unspecs for autovectorization patterns.
	* config/riscv/vector.md: Remove include of vector-iterators.md
	and include vector-auto.md.
---
 gcc/config/riscv/riscv.md            |  1 +
 gcc/config/riscv/vector-auto.md      | 79 ++++++++++++++++++++++++++++
 gcc/config/riscv/vector-iterators.md |  2 +
 gcc/config/riscv/vector.md           |  4 +-
 4 files changed, 84 insertions(+), 2 deletions(-)
 create mode 100644 gcc/config/riscv/vector-auto.md

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index bc384d9aedf..7f8f3a6cb18 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -135,6 +135,7 @@
 (include "predicates.md")
 (include "constraints.md")
 (include "iterators.md")
+(include "vector-iterators.md")
 
 ;; ....................
 ;;
diff --git a/gcc/config/riscv/vector-auto.md b/gcc/config/riscv/vector-auto.md
new file mode 100644
index 00000000000..dc62f9af705
--- /dev/null
+++ b/gcc/config/riscv/vector-auto.md
@@ -0,0 +1,79 @@
+;; Machine description for RISC-V 'V' Extension for GNU compiler.
+;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
+;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+;; Contributed by Michael Collison (collison@rivosinc.com, Rivos Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3.  If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] Addition
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vadd.vv
+;; - vadd.vx
+;; - vadd.vi
+;; -------------------------------------------------------------------------
+
+(define_expand "<optab><mode>3"
+  [(set (match_operand:VI 0 "register_operand")
+	(any_int_binop:VI (match_operand:VI 1 "register_operand")
+			  (match_operand:VI 2 "register_operand")))]
+  "TARGET_VECTOR"
+{
+  using namespace riscv_vector;
+
+  rtx merge = RVV_VUNDEF (<MODE>mode);
+  rtx vl = gen_reg_rtx (Pmode);
+  emit_vlmax_vsetvl (<MODE>mode, vl);
+  rtx mask_policy = get_mask_policy_no_pred();
+  rtx tail_policy = get_tail_policy_no_pred();
+  rtx mask = CONSTM1_RTX(<VM>mode);
+  rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+  emit_insn(gen_pred_<optab><mode>(operands[0], mask, merge, operands[1], operands[2],
+				vl, tail_policy, mask_policy, vlmax_avl_p));
+
+  DONE;
+})
+
+(define_expand "cond_<optab><mode>3"
+  [(set (match_operand:VI 0 "register_operand")
+	(if_then_else:VI
+	 (unspec:<VM>
+	  [(match_operand:<VM> 1 "register_operand")] UNSPEC_VPREDICATE)
+	 (any_int_binop:VI
+	  (match_operand:VI 2 "register_operand")
+	  (match_operand:VI 3 "register_operand"))
+	 (match_operand:VI 4 "register_operand")))]
+  "TARGET_VECTOR"
+{
+  using namespace riscv_vector;
+
+  rtx merge = operands[4];
+  rtx vl = gen_reg_rtx (Pmode);
+  emit_vlmax_vsetvl (<MODE>mode, vl);
+  rtx mask_policy = get_mask_policy_no_pred();
+  rtx tail_policy = get_tail_policy_no_pred();
+  rtx mask = operands[1];
+  rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+  emit_insn(gen_pred_<optab><mode>(operands[0], mask, merge, operands[2], operands[3],
+				vl, tail_policy, mask_policy, vlmax_avl_p));
+  DONE;
+})
+
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 70ad85b661b..7fae87968d7 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -34,6 +34,8 @@
   UNSPEC_VMULHU
   UNSPEC_VMULHSU
 
+  UNSPEC_VADD
+  UNSPEC_VSUB
   UNSPEC_VADC
   UNSPEC_VSBC
   UNSPEC_VMADC
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0ecca98f20c..2ac5b744503 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -26,8 +26,6 @@
 ;; - Auto-vectorization (TBD)
 ;; - Combine optimization (TBD)
 
-(include "vector-iterators.md")
-
 (define_constants [
    (INVALID_ATTRIBUTE            255)
    (X0_REGNUM                      0)
@@ -351,6 +349,8 @@
 	   (symbol_ref "INTVAL (operands[4])")]
 	(const_int INVALID_ATTRIBUTE)))
 
+(include "vector-auto.md")
+
 ;; -----------------------------------------------------------------
 ;; ---- Miscellaneous Operations
 ;; -----------------------------------------------------------------
-- 
2.34.1