From: Michael Collison <collison@rivosinc.com>
To: gcc-patches@gcc.gnu.org
Subject: [PATCH v4 06/10] RISC-V:autovec: Add autovectorization tests for add & sub
Date: Mon, 17 Apr 2023 14:36:57 -0400 [thread overview]
Message-ID: <20230417183701.2249183-7-collison@rivosinc.com> (raw)
In-Reply-To: <20230417183701.2249183-1-collison@rivosinc.com>
2023-03-02 Michael Collison <collison@rivosinc.com>
Vineet Gupta <vineetg@rivosinc.com>
* gcc.target/riscv/rvv/autovec: New directory
for autovectorization tests.
* gcc.target/riscv/rvv/autovec/loop-add-rv32.c: New
test to verify code generation of vector add on rv32.
* gcc.target/riscv/rvv/autovec/loop-add.c: New
test to verify code generation of vector add on rv64.
* gcc.target/riscv/rvv/autovec/loop-sub-rv32.c: New
test to verify code generation of vector subtract on rv32.
* gcc.target/riscv/rvv/autovec/loop-sub.c: New
test to verify code generation of vector subtract on rv64.
---
.../riscv/rvv/autovec/loop-add-rv32.c | 24 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-add.c | 24 +++++++++++++++++++
.../riscv/rvv/autovec/loop-sub-rv32.c | 24 +++++++++++++++++++
.../gcc.target/riscv/rvv/autovec/loop-sub.c | 24 +++++++++++++++++++
4 files changed, 96 insertions(+)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
new file mode 100644
index 00000000000..bdc3b6892e9
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] + b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
new file mode 100644
index 00000000000..d7f992c7d27
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-add.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] + b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvadd\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
new file mode 100644
index 00000000000..7d0a40ec539
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub-rv32.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv32gcv -mabi=ilp32d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] - b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
new file mode 100644
index 00000000000..c8900884f83
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/loop-sub.c
@@ -0,0 +1,24 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O2 -ftree-vectorize -march=rv64gcv -mabi=lp64d" } */
+
+#include <stdint.h>
+
+#define TEST_TYPE(TYPE) \
+ void vadd_##TYPE (TYPE *dst, TYPE *a, TYPE *b, int n) \
+ { \
+ for (int i = 0; i < n; i++) \
+ dst[i] = a[i] - b[i]; \
+ }
+
+/* *int8_t not autovec currently. */
+#define TEST_ALL() \
+ TEST_TYPE(int16_t) \
+ TEST_TYPE(uint16_t) \
+ TEST_TYPE(int32_t) \
+ TEST_TYPE(uint32_t) \
+ TEST_TYPE(int64_t) \
+ TEST_TYPE(uint64_t)
+
+TEST_ALL()
+
+/* { dg-final { scan-assembler-times {\tvsub\.vv} 6 } } */
--
2.34.1
next prev parent reply other threads:[~2023-04-17 18:37 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-17 18:36 [PATCH v4 00/10] RISC-V: Add autovec support Michael Collison
2023-04-17 18:36 ` [PATCH v4 01/10] RISC-V: Add new predicates and function prototypes Michael Collison
2023-04-19 0:54 ` Kito Cheng
2023-04-26 2:50 ` Jeff Law
2023-04-17 18:36 ` [PATCH v4 02/10] RISC-V: autovec: Export policy functions to global scope Michael Collison
2023-04-17 18:36 ` [PATCH v4 03/10] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
2023-04-19 1:15 ` Kito Cheng
2023-04-20 2:19 ` juzhe.zhong
2023-04-17 18:36 ` [PATCH v4 04/10] RISC-V:autovec: Add target vectorization hooks Michael Collison
2023-04-19 1:04 ` Kito Cheng
2023-04-20 2:11 ` juzhe.zhong
2023-04-17 18:36 ` [PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations Michael Collison
2023-04-18 23:14 ` Jeff Law
2023-04-19 1:19 ` Kito Cheng
2023-04-20 20:21 ` Michael Collison
2023-04-20 2:24 ` juzhe.zhong
2023-04-26 18:15 ` Robin Dapp
[not found] ` <3DF5ADD87A33EE11+BA2E4625-72A4-421A-B9D3-6DCA48E402BD@rivai.ai>
2023-04-27 0:04 ` [PATCH v4 05/10] RISC-V: autovec: " Michael Collison
2023-04-27 16:20 ` Palmer Dabbelt
2023-04-17 18:36 ` Michael Collison [this message]
2023-04-17 18:36 ` [PATCH v4 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
2023-04-18 6:11 ` Richard Biener
2023-04-18 14:28 ` Kito Cheng
2023-04-18 18:21 ` Kito Cheng
2023-04-18 22:48 ` juzhe.zhong
2023-04-18 23:19 ` Michael Collison
2023-04-20 10:01 ` Richard Sandiford
2023-04-17 18:36 ` [PATCH v4 08/10] RISC-V:autovec: Add autovectorization tests for binary integer Michael Collison
2023-04-17 18:37 ` [PATCH v4 09/10] This patch adds a guard for VNx1 vectors that are present in ports like riscv Michael Collison
2023-04-18 14:26 ` Kito Cheng
2023-04-18 18:10 ` Michael Collison
2023-04-17 18:37 ` [PATCH v4 10/10] This patch supports 8 bit auto-vectorization in riscv Michael Collison
2023-04-17 19:26 ` [PATCH v4 00/10] RISC-V: Add autovec support Palmer Dabbelt
2023-04-18 6:22 ` Richard Biener
2023-04-25 15:26 ` Palmer Dabbelt
2023-04-26 2:52 ` Jeff Law
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