From: "juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>
To: collison <collison@rivosinc.com>, gcc-patches <gcc-patches@gcc.gnu.org>
Cc: jeffreyalaw <jeffreyalaw@gmail.com>,
Kito.cheng <Kito.cheng@sifive.com>,
kito.cheng <kito.cheng@gmail.com>, palmer <palmer@dabbelt.com>,
palmer <palmer@rivosinc.com>,
"Richard Biener" <richard.guenther@gmail.com>
Subject: Re: [PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations
Date: Thu, 20 Apr 2023 10:24:17 +0800 [thread overview]
Message-ID: <38A0D0C38DD3239E+2023042010241661230530@rivai.ai> (raw)
In-Reply-To: <20230417183701.2249183-6-collison@rivosinc.com>
[-- Attachment #1: Type: text/plain, Size: 6375 bytes --]
1. We should only support len_load/len_store in the first patch before any other auto-vectorization operation.
I have sent the patch:
https://gcc.gnu.org/pipermail/gcc-patches/2023-April/616223.html
2. cond_<optab><mode> is the conditional auto-vectorization pattern used by reduction operation and comparison selecting.
If we don't have reduce_* pattern and VCOND/VEC_CMP/... patterns, we should not have them now.
3.+ rtx merge = RVV_VUNDEF (<MODE>mode);
+ rtx vl = gen_reg_rtx (Pmode);
+ emit_vlmax_vsetvl (<MODE>mode, vl);
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = CONSTM1_RTX(<VM>mode);
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
These operands preparation codes should be added into a wrapper.
How to add a wrapper, you can reference "emit_nonvlmax_op" , "emit_pred_op"... functions.
Thanks.
juzhe.zhong@rivai.ai
From: Michael Collison
Date: 2023-04-18 02:36
To: gcc-patches
Subject: [PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations
2023-03-02 Michael Collison <collison@rivosinc.com>
Juzhe Zhong <juzhe.zhong@rivai.ai>
* config/riscv/riscv.md (riscv_vector_preferred_simd_mode): Include
vector-iterators.md.
* config/riscv/vector-auto.md: New file containing
autovectorization patterns.
* config/riscv/vector-iterators.md (UNSPEC_VADD/UNSPEC_VSUB):
New unspecs for autovectorization patterns.
* config/riscv/vector.md: Remove include of vector-iterators.md
and include vector-auto.md.
---
gcc/config/riscv/riscv.md | 1 +
gcc/config/riscv/vector-auto.md | 79 ++++++++++++++++++++++++++++
gcc/config/riscv/vector-iterators.md | 2 +
gcc/config/riscv/vector.md | 4 +-
4 files changed, 84 insertions(+), 2 deletions(-)
create mode 100644 gcc/config/riscv/vector-auto.md
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index bc384d9aedf..7f8f3a6cb18 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -135,6 +135,7 @@
(include "predicates.md")
(include "constraints.md")
(include "iterators.md")
+(include "vector-iterators.md")
;; ....................
;;
diff --git a/gcc/config/riscv/vector-auto.md b/gcc/config/riscv/vector-auto.md
new file mode 100644
index 00000000000..dc62f9af705
--- /dev/null
+++ b/gcc/config/riscv/vector-auto.md
@@ -0,0 +1,79 @@
+;; Machine description for RISC-V 'V' Extension for GNU compiler.
+;; Copyright (C) 2022-2023 Free Software Foundation, Inc.
+;; Contributed by Juzhe Zhong (juzhe.zhong@rivai.ai), RiVAI Technologies Ltd.
+;; Contributed by Michael Collison (collison@rivosinc.com, Rivos Inc.
+
+;; This file is part of GCC.
+
+;; GCC is free software; you can redistribute it and/or modify
+;; it under the terms of the GNU General Public License as published by
+;; the Free Software Foundation; either version 3, or (at your option)
+;; any later version.
+
+;; GCC is distributed in the hope that it will be useful,
+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+;; GNU General Public License for more details.
+
+;; You should have received a copy of the GNU General Public License
+;; along with GCC; see the file COPYING3. If not see
+;; <http://www.gnu.org/licenses/>.
+
+
+;; -------------------------------------------------------------------------
+;; ---- [INT] Addition
+;; -------------------------------------------------------------------------
+;; Includes:
+;; - vadd.vv
+;; - vadd.vx
+;; - vadd.vi
+;; -------------------------------------------------------------------------
+
+(define_expand "<optab><mode>3"
+ [(set (match_operand:VI 0 "register_operand")
+ (any_int_binop:VI (match_operand:VI 1 "register_operand")
+ (match_operand:VI 2 "register_operand")))]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = RVV_VUNDEF (<MODE>mode);
+ rtx vl = gen_reg_rtx (Pmode);
+ emit_vlmax_vsetvl (<MODE>mode, vl);
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = CONSTM1_RTX(<VM>mode);
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+ emit_insn(gen_pred_<optab><mode>(operands[0], mask, merge, operands[1], operands[2],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+
+ DONE;
+})
+
+(define_expand "cond_<optab><mode>3"
+ [(set (match_operand:VI 0 "register_operand")
+ (if_then_else:VI
+ (unspec:<VM>
+ [(match_operand:<VM> 1 "register_operand")] UNSPEC_VPREDICATE)
+ (any_int_binop:VI
+ (match_operand:VI 2 "register_operand")
+ (match_operand:VI 3 "register_operand"))
+ (match_operand:VI 4 "register_operand")))]
+ "TARGET_VECTOR"
+{
+ using namespace riscv_vector;
+
+ rtx merge = operands[4];
+ rtx vl = gen_reg_rtx (Pmode);
+ emit_vlmax_vsetvl (<MODE>mode, vl);
+ rtx mask_policy = get_mask_policy_no_pred();
+ rtx tail_policy = get_tail_policy_no_pred();
+ rtx mask = operands[1];
+ rtx vlmax_avl_p = get_avl_type_rtx(NONVLMAX);
+
+ emit_insn(gen_pred_<optab><mode>(operands[0], mask, merge, operands[2], operands[3],
+ vl, tail_policy, mask_policy, vlmax_avl_p));
+ DONE;
+})
+
diff --git a/gcc/config/riscv/vector-iterators.md b/gcc/config/riscv/vector-iterators.md
index 70ad85b661b..7fae87968d7 100644
--- a/gcc/config/riscv/vector-iterators.md
+++ b/gcc/config/riscv/vector-iterators.md
@@ -34,6 +34,8 @@
UNSPEC_VMULHU
UNSPEC_VMULHSU
+ UNSPEC_VADD
+ UNSPEC_VSUB
UNSPEC_VADC
UNSPEC_VSBC
UNSPEC_VMADC
diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md
index 0ecca98f20c..2ac5b744503 100644
--- a/gcc/config/riscv/vector.md
+++ b/gcc/config/riscv/vector.md
@@ -26,8 +26,6 @@
;; - Auto-vectorization (TBD)
;; - Combine optimization (TBD)
-(include "vector-iterators.md")
-
(define_constants [
(INVALID_ATTRIBUTE 255)
(X0_REGNUM 0)
@@ -351,6 +349,8 @@
(symbol_ref "INTVAL (operands[4])")]
(const_int INVALID_ATTRIBUTE)))
+(include "vector-auto.md")
+
;; -----------------------------------------------------------------
;; ---- Miscellaneous Operations
;; -----------------------------------------------------------------
--
2.34.1
next prev parent reply other threads:[~2023-04-20 2:24 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-17 18:36 [PATCH v4 00/10] RISC-V: Add autovec support Michael Collison
2023-04-17 18:36 ` [PATCH v4 01/10] RISC-V: Add new predicates and function prototypes Michael Collison
2023-04-19 0:54 ` Kito Cheng
2023-04-26 2:50 ` Jeff Law
2023-04-17 18:36 ` [PATCH v4 02/10] RISC-V: autovec: Export policy functions to global scope Michael Collison
2023-04-17 18:36 ` [PATCH v4 03/10] RISC-V:autovec: Add auto-vectorization support functions Michael Collison
2023-04-19 1:15 ` Kito Cheng
2023-04-20 2:19 ` juzhe.zhong
2023-04-17 18:36 ` [PATCH v4 04/10] RISC-V:autovec: Add target vectorization hooks Michael Collison
2023-04-19 1:04 ` Kito Cheng
2023-04-20 2:11 ` juzhe.zhong
2023-04-17 18:36 ` [PATCH v4 05/10] RISC-V:autovec: Add autovectorization patterns for binary integer operations Michael Collison
2023-04-18 23:14 ` Jeff Law
2023-04-19 1:19 ` Kito Cheng
2023-04-20 20:21 ` Michael Collison
2023-04-20 2:24 ` juzhe.zhong [this message]
2023-04-26 18:15 ` Robin Dapp
[not found] ` <3DF5ADD87A33EE11+BA2E4625-72A4-421A-B9D3-6DCA48E402BD@rivai.ai>
2023-04-27 0:04 ` [PATCH v4 05/10] RISC-V: autovec: " Michael Collison
2023-04-27 16:20 ` Palmer Dabbelt
2023-04-17 18:36 ` [PATCH v4 06/10] RISC-V:autovec: Add autovectorization tests for add & sub Michael Collison
2023-04-17 18:36 ` [PATCH v4 07/10] vect: Verify that GET_MODE_NUNITS is a multiple of 2 Michael Collison
2023-04-18 6:11 ` Richard Biener
2023-04-18 14:28 ` Kito Cheng
2023-04-18 18:21 ` Kito Cheng
2023-04-18 22:48 ` juzhe.zhong
2023-04-18 23:19 ` Michael Collison
2023-04-20 10:01 ` Richard Sandiford
2023-04-17 18:36 ` [PATCH v4 08/10] RISC-V:autovec: Add autovectorization tests for binary integer Michael Collison
2023-04-17 18:37 ` [PATCH v4 09/10] This patch adds a guard for VNx1 vectors that are present in ports like riscv Michael Collison
2023-04-18 14:26 ` Kito Cheng
2023-04-18 18:10 ` Michael Collison
2023-04-17 18:37 ` [PATCH v4 10/10] This patch supports 8 bit auto-vectorization in riscv Michael Collison
2023-04-17 19:26 ` [PATCH v4 00/10] RISC-V: Add autovec support Palmer Dabbelt
2023-04-18 6:22 ` Richard Biener
2023-04-25 15:26 ` Palmer Dabbelt
2023-04-26 2:52 ` Jeff Law
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