[PATCH v1] RISC-V: Fix one bug for floating-point static frm

[PATCH v1] RISC-V: Fix one bug for floating-point static frm

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to fix one bug to align below items of spec.

1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.

When mode switching the function entry and exit, it will take DYN as
the frm mode.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
	when FRM_MODE_DYN.
	(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
	(riscv_mode_exit): Likewise for exit mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
 gcc/config/riscv/riscv.cc                     |  6 ++--
 .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
 2 files changed, 34 insertions(+), 3 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..f5fe910426e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
 	emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
 	{
 	  rtx scaler = gen_reg_rtx (SImode);
 	  rtx imm = gen_int_mode (mode, SImode);
@@ -7774,7 +7774,7 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7791,7 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
-- 
2.34.1

Re: [PATCH v1] RISC-V: Fix one bug for floating-point static frm

[juzhe.zhong]

[-- Attachment #1: Type: text/plain, Size: 3524 bytes --]

LGTM



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-07-04 13:50
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v1] RISC-V: Fix one bug for floating-point static frm
From: Pan Li <pan2.li@intel.com>
 
This patch would like to fix one bug to align below items of spec.
 
1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.
 
When mode switching the function entry and exit, it will take DYN as
the frm mode.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
 
gcc/ChangeLog:
 
* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
when FRM_MODE_DYN.
(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
(riscv_mode_exit): Likewise for exit mode.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
gcc/config/riscv/riscv.cc                     |  6 ++--
.../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
2 files changed, 34 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..f5fe910426e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
{
  rtx scaler = gen_reg_rtx (SImode);
  rtx imm = gen_int_mode (mode, SImode);
@@ -7774,7 +7774,7 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7791,7 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
-- 
2.34.1
 
 

RE: [PATCH v1] RISC-V: Fix one bug for floating-point static frm

[Li, Pan2]

[-- Attachment #1: Type: text/plain, Size: 4406 bytes --]

Thanks Juzhe, passed all the test of riscv.exp and rvv.exp, will commit it with the reverted one with the final approval.

Pan

From: juzhe.zhong@rivai.ai <juzhe.zhong@rivai.ai>
Sent: Tuesday, July 4, 2023 1:53 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Li, Pan2 <pan2.li@intel.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: Re: [PATCH v1] RISC-V: Fix one bug for floating-point static frm

LGTM

________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-07-04 13:50
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Fix one bug for floating-point static frm
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

This patch would like to fix one bug to align below items of spec.

1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.

When mode switching the function entry and exit, it will take DYN as
the frm mode.

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
when FRM_MODE_DYN.
(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
(riscv_mode_exit): Likewise for exit mode.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
gcc/config/riscv/riscv.cc                     |  6 ++--
.../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
2 files changed, 34 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..f5fe910426e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
{
  rtx scaler = gen_reg_rtx (SImode);
  rtx imm = gen_int_mode (mode, SImode);
@@ -7774,7 +7774,7 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7791,7 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
--
2.34.1

[PATCH v2] RISC-V: Fix one bug for floating-point static frm

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to fix one bug to align below items of spec.

1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.

When mode switching the function entry and exit, it will take DYN as
the frm mode.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
	when FRM_MODE_DYN.
	(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
	(riscv_mode_exit): Likewise for exit mode.
	(riscv_mode_needed): Likewise for needed mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
 gcc/config/riscv/riscv.cc                     |  8 ++---
 .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
 2 files changed, 35 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..37f96f8a238 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
 	emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
 	{
 	  rtx scaler = gen_reg_rtx (SImode);
 	  rtx imm = gen_int_mode (mode, SImode);
@@ -7697,7 +7697,7 @@ riscv_mode_needed (int entity, rtx_insn *insn)
     case RISCV_VXRM:
       return code >= 0 ? get_attr_vxrm_mode (insn) : VXRM_MODE_NONE;
     case RISCV_FRM:
-      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
+      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7774,7 +7774,7 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7791,7 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
-- 
2.34.1

RE: [PATCH v1] RISC-V: Fix one bug for floating-point static frm

[Li, Pan2]

[-- Attachment #1: Type: text/plain, Size: 5135 bytes --]

Update PATCH V2 for DYN in needed as below.

https://gcc.gnu.org/pipermail/gcc-patches/2023-July/623543.html

Pan

From: Li, Pan2
Sent: Tuesday, July 4, 2023 2:50 PM
To: juzhe.zhong@rivai.ai; gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Robin Dapp <rdapp.gcc@gmail.com>; jeffreyalaw <jeffreyalaw@gmail.com>; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng <kito.cheng@gmail.com>
Subject: RE: [PATCH v1] RISC-V: Fix one bug for floating-point static frm

Thanks Juzhe, passed all the test of riscv.exp and rvv.exp, will commit it with the reverted one with the final approval.

Pan

From: juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai> <juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>>
Sent: Tuesday, July 4, 2023 1:53 PM
To: Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; gcc-patches <gcc-patches@gcc.gnu.org<mailto:gcc-patches@gcc.gnu.org>>
Cc: Robin Dapp <rdapp.gcc@gmail.com<mailto:rdapp.gcc@gmail.com>>; jeffreyalaw <jeffreyalaw@gmail.com<mailto:jeffreyalaw@gmail.com>>; Li, Pan2 <pan2.li@intel.com<mailto:pan2.li@intel.com>>; Wang, Yanzhang <yanzhang.wang@intel.com<mailto:yanzhang.wang@intel.com>>; kito.cheng <kito.cheng@gmail.com<mailto:kito.cheng@gmail.com>>
Subject: Re: [PATCH v1] RISC-V: Fix one bug for floating-point static frm

LGTM

________________________________
juzhe.zhong@rivai.ai<mailto:juzhe.zhong@rivai.ai>

From: pan2.li<mailto:pan2.li@intel.com>
Date: 2023-07-04 13:50
To: gcc-patches<mailto:gcc-patches@gcc.gnu.org>
CC: juzhe.zhong<mailto:juzhe.zhong@rivai.ai>; rdapp.gcc<mailto:rdapp.gcc@gmail.com>; jeffreyalaw<mailto:jeffreyalaw@gmail.com>; pan2.li<mailto:pan2.li@intel.com>; yanzhang.wang<mailto:yanzhang.wang@intel.com>; kito.cheng<mailto:kito.cheng@gmail.com>
Subject: [PATCH v1] RISC-V: Fix one bug for floating-point static frm
From: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

This patch would like to fix one bug to align below items of spec.

1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.

When mode switching the function entry and exit, it will take DYN as
the frm mode.

Signed-off-by: Pan Li <pan2.li@intel.com<mailto:pan2.li@intel.com>>

gcc/ChangeLog:

* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
when FRM_MODE_DYN.
(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
(riscv_mode_exit): Likewise for exit mode.

gcc/testsuite/ChangeLog:

* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
gcc/config/riscv/riscv.cc                     |  6 ++--
.../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
2 files changed, 34 insertions(+), 3 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..f5fe910426e 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
{
  rtx scaler = gen_reg_rtx (SImode);
  rtx imm = gen_int_mode (mode, SImode);
@@ -7774,7 +7774,7 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7791,7 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
--
2.34.1

Re: [PATCH v2] RISC-V: Fix one bug for floating-point static frm

[juzhe.zhong]

[-- Attachment #1: Type: text/plain, Size: 3948 bytes --]

LGTM.



juzhe.zhong@rivai.ai
 
From: pan2.li
Date: 2023-07-04 16:08
To: gcc-patches
CC: juzhe.zhong; rdapp.gcc; jeffreyalaw; pan2.li; yanzhang.wang; kito.cheng
Subject: [PATCH v2] RISC-V: Fix one bug for floating-point static frm
From: Pan Li <pan2.li@intel.com>
 
This patch would like to fix one bug to align below items of spec.
 
1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.
 
When mode switching the function entry and exit, it will take DYN as
the frm mode.
 
Signed-off-by: Pan Li <pan2.li@intel.com>
 
gcc/ChangeLog:
 
* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
when FRM_MODE_DYN.
(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
(riscv_mode_exit): Likewise for exit mode.
(riscv_mode_needed): Likewise for needed mode.
 
gcc/testsuite/ChangeLog:
 
* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
gcc/config/riscv/riscv.cc                     |  8 ++---
.../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
2 files changed, 35 insertions(+), 4 deletions(-)
create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
 
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..37f96f8a238 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
{
  rtx scaler = gen_reg_rtx (SImode);
  rtx imm = gen_int_mode (mode, SImode);
@@ -7697,7 +7697,7 @@ riscv_mode_needed (int entity, rtx_insn *insn)
     case RISCV_VXRM:
       return code >= 0 ? get_attr_vxrm_mode (insn) : VXRM_MODE_NONE;
     case RISCV_FRM:
-      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
+      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7774,7 +7774,7 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7791,7 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+ size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+ size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
-- 
2.34.1
 
 

Re: [PATCH v2] RISC-V: Fix one bug for floating-point static frm

[Robin Dapp]

Hi Pan,

I only just now got back to my mails and I'm a bit confused about
the several patches related to rounding mode.

> 1. By default, the RVV floating-point will take dyn mode.

Here you are referring to 10.1 in the spec I assume.  Could we
add this as a comment in the code?

> 2. DYN is invalid in FRM register for RVV floating-point.

What does that mean or rather how is that reflected in the code?

> -      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
> +      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;
This still has yesterday's bug right?  I.e. get_attr_frm_mode returns
5 for dyn instead of 7 because the enums don't match (leading to
SIGILL).

> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
> @@ -0,0 +1,31 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */

I would prefer to have an execution test here as well.  Even
though we likely FAIL in other tests when the rounding mode
is off, it would be good to have a specific one.  Maybe it
doesn't exactly fit into this patch but in general.

Regards
 Robin

RE: [PATCH v2] RISC-V: Fix one bug for floating-point static frm

[Li, Pan2]

Hi Robin,

Thanks for reviewing, sorry for my silly mistakes in the original patch, CIL.

> Here you are referring to 10.1 in the spec I assume.  Could we add this as a comment in the code?

Sure, from the spec rvv 1.0, aka "All standard vector floating-point arithmetic operations follow the IEEE-754/2008 standard. All vector floating-point operations use the dynamic rounding mode in the frm register".

> What does that mean or rather how is that reflected in the code?

This part from spec 20191213 F part, aka "111 DYN In instruction’s rm fi eld, selects dynamic rounding mode; In Rounding Mode register, Invalid.".

> This still has yesterday's bug right?  I.e. get_attr_frm_mode returns 5 for dyn instead of 7 because the enums don't match (leading to SIGILL).

Should be no, FRM_MODE_DYN is generated by vector.md, which present the mode for switching and different from the frm value defined in riscv-v.cc. However and more generally, we should have a function convert from frm_mode to frm as I understand.

> I would prefer to have an execution test here as well.  Even
> though we likely FAIL in other tests when the rounding mode
> is off, it would be good to have a specific one.  Maybe it
> doesn't exactly fit into this patch but in general.

Sure, I can file another PATCH for execution, like vfadd with RMM mode but the frm value is changed by this intrinsic, the underlying dynamic round mode can leverage this case I bet.

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Tuesday, July 4, 2023 8:52 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com
Subject: Re: [PATCH v2] RISC-V: Fix one bug for floating-point static frm

Hi Pan,

I only just now got back to my mails and I'm a bit confused about
the several patches related to rounding mode.

> 1. By default, the RVV floating-point will take dyn mode.

Here you are referring to 10.1 in the spec I assume.  Could we
add this as a comment in the code?

> 2. DYN is invalid in FRM register for RVV floating-point.

What does that mean or rather how is that reflected in the code?

> -      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
> +      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;
This still has yesterday's bug right?  I.e. get_attr_frm_mode returns
5 for dyn instead of 7 because the enums don't match (leading to
SIGILL).

> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
> @@ -0,0 +1,31 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */

I would prefer to have an execution test here as well.  Even
though we likely FAIL in other tests when the rounding mode
is off, it would be good to have a specific one.  Maybe it
doesn't exactly fit into this patch but in general.

Regards
 Robin

[PATCH v3] RISC-V: Fix one bug for floating-point static frm

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to fix one bug to align below items of spec.

1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.

When mode switching the function entry and exit, it will take DYN as
the frm mode.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
	when FRM_MODE_DYN.
	(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
	(riscv_mode_exit): Likewise for exit mode.
	(riscv_mode_needed): Likewise for needed mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
 gcc/config/riscv/riscv.cc                     | 14 ++++++---
 .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
 2 files changed, 41 insertions(+), 4 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..ebc4db1aa94 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
 	emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
 	{
 	  rtx scaler = gen_reg_rtx (SImode);
 	  rtx imm = gen_int_mode (mode, SImode);
@@ -7697,7 +7697,9 @@ riscv_mode_needed (int entity, rtx_insn *insn)
     case RISCV_VXRM:
       return code >= 0 ? get_attr_vxrm_mode (insn) : VXRM_MODE_NONE;
     case RISCV_FRM:
-      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
+      /* According to RVV 1.0 spec, all vector floating-point operations use
+	 the dynamic rounding mode in the frm register.  */
+      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7774,7 +7776,9 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      /* According to RVV 1.0 spec, all vector floating-point operations use
+	 the dynamic rounding mode in the frm register.  */
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7795,9 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      /* According to RVV 1.0 spec, all vector floating-point operations use
+	 the dynamic rounding mode in the frm register.  */
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
-- 
2.34.1

[PATCH v4] RISC-V: Fix one bug for floating-point static frm

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to fix one bug to align below items of spec.

1. By default, the RVV floating-point will take dyn mode.
2. DYN is invalid in FRM register for RVV floating-point.

When mode switching the function entry and exit, it will take DYN as
the frm mode.

Signed-off-by: Pan Li <pan2.li@intel.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
	when FRM_MODE_DYN.
	(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
	(riscv_mode_exit): Likewise for exit mode.
	(riscv_mode_needed): Likewise for needed mode.
	(riscv_mode_after): Likewise for after mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
 gcc/config/riscv/riscv.cc                     | 16 +++++++---
 .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
 2 files changed, 42 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..4db32de5696 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
 	emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
 	{
 	  rtx scaler = gen_reg_rtx (SImode);
 	  rtx imm = gen_int_mode (mode, SImode);
@@ -7697,7 +7697,9 @@ riscv_mode_needed (int entity, rtx_insn *insn)
     case RISCV_VXRM:
       return code >= 0 ? get_attr_vxrm_mode (insn) : VXRM_MODE_NONE;
     case RISCV_FRM:
-      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
+      /* According to RVV 1.0 spec, all vector floating-point operations use
+	 the dynamic rounding mode in the frm register.  */
+      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7757,7 +7759,7 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn)
     case RISCV_FRM:
       return riscv_entity_mode_after (FRM_REGNUM, insn, mode,
 				      (int (*)(rtx_insn *)) get_attr_frm_mode,
-				      FRM_MODE_NONE);
+				      FRM_MODE_DYN);
     default:
       gcc_unreachable ();
     }
@@ -7774,7 +7776,9 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      /* According to RVV 1.0 spec, all vector floating-point operations use
+	 the dynamic rounding mode in the frm register.  */
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7795,9 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      /* According to RVV 1.0 spec, all vector floating-point operations use
+	 the dynamic rounding mode in the frm register.  */
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
-- 
2.34.1

Re: [PATCH v4] RISC-V: Fix one bug for floating-point static frm

[Kito Cheng]

LGTM, thanks :)

On Wed, Jul 5, 2023 at 3:03 PM Pan Li via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> From: Pan Li <pan2.li@intel.com>
>
> This patch would like to fix one bug to align below items of spec.
>
> 1. By default, the RVV floating-point will take dyn mode.
> 2. DYN is invalid in FRM register for RVV floating-point.
>
> When mode switching the function entry and exit, it will take DYN as
> the frm mode.
>
> Signed-off-by: Pan Li <pan2.li@intel.com>
>
> gcc/ChangeLog:
>
>         * config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
>         when FRM_MODE_DYN.
>         (riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
>         (riscv_mode_exit): Likewise for exit mode.
>         (riscv_mode_needed): Likewise for needed mode.
>         (riscv_mode_after): Likewise for after mode.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
> ---
>  gcc/config/riscv/riscv.cc                     | 16 +++++++---
>  .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
>  2 files changed, 42 insertions(+), 5 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
>
> diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
> index e4dc8115e69..4db32de5696 100644
> --- a/gcc/config/riscv/riscv.cc
> +++ b/gcc/config/riscv/riscv.cc
> @@ -7670,7 +7670,7 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
>         emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
>        break;
>      case RISCV_FRM:
> -      if (mode != FRM_MODE_NONE && mode != prev_mode)
> +      if (mode != FRM_MODE_DYN && mode != prev_mode)
>         {
>           rtx scaler = gen_reg_rtx (SImode);
>           rtx imm = gen_int_mode (mode, SImode);
> @@ -7697,7 +7697,9 @@ riscv_mode_needed (int entity, rtx_insn *insn)
>      case RISCV_VXRM:
>        return code >= 0 ? get_attr_vxrm_mode (insn) : VXRM_MODE_NONE;
>      case RISCV_FRM:
> -      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
> +      /* According to RVV 1.0 spec, all vector floating-point operations use
> +        the dynamic rounding mode in the frm register.  */
> +      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;
>      default:
>        gcc_unreachable ();
>      }
> @@ -7757,7 +7759,7 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn)
>      case RISCV_FRM:
>        return riscv_entity_mode_after (FRM_REGNUM, insn, mode,
>                                       (int (*)(rtx_insn *)) get_attr_frm_mode,
> -                                     FRM_MODE_NONE);
> +                                     FRM_MODE_DYN);
>      default:
>        gcc_unreachable ();
>      }
> @@ -7774,7 +7776,9 @@ riscv_mode_entry (int entity)
>      case RISCV_VXRM:
>        return VXRM_MODE_NONE;
>      case RISCV_FRM:
> -      return FRM_MODE_NONE;
> +      /* According to RVV 1.0 spec, all vector floating-point operations use
> +        the dynamic rounding mode in the frm register.  */
> +      return FRM_MODE_DYN;
>      default:
>        gcc_unreachable ();
>      }
> @@ -7791,7 +7795,9 @@ riscv_mode_exit (int entity)
>      case RISCV_VXRM:
>        return VXRM_MODE_NONE;
>      case RISCV_FRM:
> -      return FRM_MODE_NONE;
> +      /* According to RVV 1.0 spec, all vector floating-point operations use
> +        the dynamic rounding mode in the frm register.  */
> +      return FRM_MODE_DYN;
>      default:
>        gcc_unreachable ();
>      }
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
> new file mode 100644
> index 00000000000..6d896e0953e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
> @@ -0,0 +1,31 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
> +
> +#include "riscv_vector.h"
> +
> +typedef float float32_t;
> +
> +vfloat32m1_t
> +test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
> +  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
> +                        size_t vl) {
> +  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
> +  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
> +}
> +
> +vfloat32m1_t
> +test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
> +                        size_t vl) {
> +  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
> +}
> +
> +/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
> +/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
> --
> 2.34.1
>

Re: [PATCH v4] RISC-V: Fix one bug for floating-point static frm

[Robin Dapp]

> LGTM, thanks :)

just a moment please, I still wanted to reply ;)

Regards
 Robin

Re: [PATCH v4] RISC-V: Fix one bug for floating-point static frm

[Kito Cheng]

On Wed, Jul 5, 2023 at 3:12 PM Robin Dapp via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> > LGTM, thanks :)
>
> just a moment please, I still wanted to reply ;)

Sure :)

>
> Regards
>  Robin
>

RE: [PATCH v4] RISC-V: Fix one bug for floating-point static frm

[Li, Pan2]

Thanks Robin, it passed all tests of riscv.exp and rvv.exp from my side. Could you please help to double confirm the issue you meet is resolved or not?

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Wednesday, July 5, 2023 3:11 PM
To: Kito Cheng <kito.cheng@gmail.com>; Li, Pan2 <pan2.li@intel.com>
Cc: rdapp.gcc@gmail.com; gcc-patches@gcc.gnu.org; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>
Subject: Re: [PATCH v4] RISC-V: Fix one bug for floating-point static frm

> LGTM, thanks :)

just a moment please, I still wanted to reply ;)

Regards
 Robin

Re: [PATCH v4] RISC-V: Fix one bug for floating-point static frm

[Robin Dapp]

Hi Pan,

yes, the problem is fixed for me.  Still some comments ;)  Sorry
it took a while.

> 1. By default, the RVV floating-point will take dyn mode.
> 2. DYN is invalid in FRM register for RVV floating-point.
> 
> When mode switching the function entry and exit, it will take DYN as
> the frm mode.

We need to clarify this as it is misleading (even if it's just
a patch description, at least I was confused):

RVV floating-point instructions always (implicitly) use the dynamic
rounding mode.  That's IMHO not a default but rather an unchangeable
fact.  This implies that rounding is performed according to the
rounding mode set in the FRM register.  The FRM register itself
only holds proper rounding modes and never the dynamic rounding mode. 

> -      if (mode != FRM_MODE_NONE && mode != prev_mode)
> +      if (mode != FRM_MODE_DYN && mode != prev_mode)
>  	{

Adding a comment like "Switching to the dynamic rounding mode is not
necessary.  When an instruction requests it, it effectively uses
the rounding mode already set in the FRM register.  All other rounding
modes require us to switch the rounding mode via the FRM register."

> -      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
> +      /* According to RVV 1.0 spec, all vector floating-point operations use
> +	 the dynamic rounding mode in the frm register.  */
> +      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;

As you reverted the previous patch get_attr_frm_mode is no longer
problematic because it returns FRM_MODE_NONE for instructions with
a dynamic rounding mode (instead of FRM_MODE_DYN).  I still find
that a bit confusing or at least halfway inconsistent and somebody
reading it will suppose something is wrong.  Could you either fix
the enum or add a TODO here that explains the situation?

The normal flow is that mode switching asks us if we need a mode
switch for an instruction and returning "NO MODE" means no.  But
we return FRM_MODE_DYN by default and FRM_MODE_NONE for vector float
which appears odd.

In riscv_mode_after the default mode is again FRM_MODE_NONE.  Wouldn't
we also want FRM_MODE_DYN here?

> @@ -7791,7 +7795,9 @@ riscv_mode_exit (int entity)
>      case RISCV_VXRM:
>        return VXRM_MODE_NONE;
>      case RISCV_FRM:
> -      return FRM_MODE_NONE;
> +      /* According to RVV 1.0 spec, all vector floating-point operations use
> +	 the dynamic rounding mode in the frm register.  */
> +      return FRM_MODE_DYN;

I'd rather not have the comment duplicated all over the place.  I
know I asked for it but I'd rather have it at a single spot explaining
what we need to do.

Regards
 Robin

RE: [PATCH v4] RISC-V: Fix one bug for floating-point static frm

[Li, Pan2]

Thanks Robin for reviewing, will address the comments with PATCH v5 later as I am in the middle of sth.

> In riscv_mode_after the default mode is again FRM_MODE_NONE.  Wouldn't
> we also want FRM_MODE_DYN here?
All of FRM should be aligned to DYN in PATCH v4, will double check about it when prepare the v5.

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Wednesday, July 5, 2023 4:03 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com
Subject: Re: [PATCH v4] RISC-V: Fix one bug for floating-point static frm

Hi Pan,

yes, the problem is fixed for me.  Still some comments ;)  Sorry
it took a while.

> 1. By default, the RVV floating-point will take dyn mode.
> 2. DYN is invalid in FRM register for RVV floating-point.
> 
> When mode switching the function entry and exit, it will take DYN as
> the frm mode.

We need to clarify this as it is misleading (even if it's just
a patch description, at least I was confused):

RVV floating-point instructions always (implicitly) use the dynamic
rounding mode.  That's IMHO not a default but rather an unchangeable
fact.  This implies that rounding is performed according to the
rounding mode set in the FRM register.  The FRM register itself
only holds proper rounding modes and never the dynamic rounding mode. 

> -      if (mode != FRM_MODE_NONE && mode != prev_mode)
> +      if (mode != FRM_MODE_DYN && mode != prev_mode)
>  	{

Adding a comment like "Switching to the dynamic rounding mode is not
necessary.  When an instruction requests it, it effectively uses
the rounding mode already set in the FRM register.  All other rounding
modes require us to switch the rounding mode via the FRM register."

> -      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
> +      /* According to RVV 1.0 spec, all vector floating-point operations use
> +	 the dynamic rounding mode in the frm register.  */
> +      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;

As you reverted the previous patch get_attr_frm_mode is no longer
problematic because it returns FRM_MODE_NONE for instructions with
a dynamic rounding mode (instead of FRM_MODE_DYN).  I still find
that a bit confusing or at least halfway inconsistent and somebody
reading it will suppose something is wrong.  Could you either fix
the enum or add a TODO here that explains the situation?

The normal flow is that mode switching asks us if we need a mode
switch for an instruction and returning "NO MODE" means no.  But
we return FRM_MODE_DYN by default and FRM_MODE_NONE for vector float
which appears odd.

In riscv_mode_after the default mode is again FRM_MODE_NONE.  Wouldn't
we also want FRM_MODE_DYN here?

> @@ -7791,7 +7795,9 @@ riscv_mode_exit (int entity)
>      case RISCV_VXRM:
>        return VXRM_MODE_NONE;
>      case RISCV_FRM:
> -      return FRM_MODE_NONE;
> +      /* According to RVV 1.0 spec, all vector floating-point operations use
> +	 the dynamic rounding mode in the frm register.  */
> +      return FRM_MODE_DYN;

I'd rather not have the comment duplicated all over the place.  I
know I asked for it but I'd rather have it at a single spot explaining
what we need to do.

Regards
 Robin

[PATCH v5] RISC-V: Fix one bug for floating-point static frm

[pan2.li]

From: Pan Li <pan2.li@intel.com>

This patch would like to fix one bug to align below items of spec.

RVV floating-point instructions always (implicitly) use the dynamic
rounding mode.  This implies that rounding is performed according to the
rounding mode set in the FRM register.  The FRM register itself
only holds proper rounding modes and never the dynamic rounding mode.

Signed-off-by: Pan Li <pan2.li@intel.com>
Co-Authored-By: Robin Dapp <rdapp@ventanamicro.com>

gcc/ChangeLog:

	* config/riscv/riscv.cc (riscv_emit_mode_set): Avoid emit insn
	when FRM_MODE_DYN.
	(riscv_mode_entry): Take FRM_MODE_DYN as entry mode.
	(riscv_mode_exit): Likewise for exit mode.
	(riscv_mode_needed): Likewise for needed mode.
	(riscv_mode_after): Likewise for after mode.

gcc/testsuite/ChangeLog:

	* gcc.target/riscv/rvv/base/float-point-frm-insert-6.c: New test.
---
 gcc/config/riscv/riscv.cc                     | 27 +++++++++++++---
 .../riscv/rvv/base/float-point-frm-insert-6.c | 31 +++++++++++++++++++
 2 files changed, 53 insertions(+), 5 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c

diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index e4dc8115e69..38d8eb2fcf5 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7670,8 +7670,19 @@ riscv_emit_mode_set (int entity, int mode, int prev_mode,
 	emit_insn (gen_vxrmsi (gen_int_mode (mode, SImode)));
       break;
     case RISCV_FRM:
-      if (mode != FRM_MODE_NONE && mode != prev_mode)
+      /* Switching to the dynamic rounding mode is not necessary.  When an
+	 instruction requests it, it effectively uses the rounding mode already
+	 set in the FRM register.  All other rounding modes require us to
+	 switch the rounding mode via the FRM register.  */
+      if (mode != FRM_MODE_DYN && mode != prev_mode)
 	{
+	  /* TODO: By design, FRM_MODE_xxx used by mode switch which is
+	     different from the FRM value like FRM_RTZ defined in
+	     riscv-protos.h.  When mode switching we actually need a conversion
+	     function to convert the mode of mode switching to the actual
+	     FRM value like FRM_RTZ.  For now, the value between the mode of
+	     mode swith and the FRM value in riscv-protos.h take the same value,
+	     and then we leverage this assumption when emit.  */
 	  rtx scaler = gen_reg_rtx (SImode);
 	  rtx imm = gen_int_mode (mode, SImode);
 
@@ -7697,7 +7708,10 @@ riscv_mode_needed (int entity, rtx_insn *insn)
     case RISCV_VXRM:
       return code >= 0 ? get_attr_vxrm_mode (insn) : VXRM_MODE_NONE;
     case RISCV_FRM:
-      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_NONE;
+      /* TODO: Here we may return FRM_MODE_NONE from get_attr_frm_mode, as well
+	 as FRM_MODE_DYN as default.  It is kind of inconsistent and we will
+	 take care of it after dynamic rounding mode.  */
+      return code >= 0 ? get_attr_frm_mode (insn) : FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7757,7 +7771,7 @@ riscv_mode_after (int entity, int mode, rtx_insn *insn)
     case RISCV_FRM:
       return riscv_entity_mode_after (FRM_REGNUM, insn, mode,
 				      (int (*)(rtx_insn *)) get_attr_frm_mode,
-				      FRM_MODE_NONE);
+				      FRM_MODE_DYN);
     default:
       gcc_unreachable ();
     }
@@ -7774,7 +7788,10 @@ riscv_mode_entry (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      /* According to RVV 1.0 spec, all vector floating-point operations use
+	 the dynamic rounding mode in the frm register.  Likewise in other
+	 similar places.  */
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
@@ -7791,7 +7808,7 @@ riscv_mode_exit (int entity)
     case RISCV_VXRM:
       return VXRM_MODE_NONE;
     case RISCV_FRM:
-      return FRM_MODE_NONE;
+      return FRM_MODE_DYN;
     default:
       gcc_unreachable ();
     }
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
new file mode 100644
index 00000000000..6d896e0953e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-frm-insert-6.c
@@ -0,0 +1,31 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gcv -mabi=lp64 -O3 -Wno-psabi" } */
+
+#include "riscv_vector.h"
+
+typedef float float32_t;
+
+vfloat32m1_t
+test_riscv_vfadd_vv_f32m1_rm (vfloat32m1_t op1, vfloat32m1_t op2, size_t vl) {
+  return __riscv_vfadd_vv_f32m1_rm (op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vv_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, vfloat32m1_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vv_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_rm(vfloat32m1_t op1, float32_t op2, size_t vl) {
+  return __riscv_vfadd_vf_f32m1_rm(op1, op2, 7, vl);
+}
+
+vfloat32m1_t
+test_vfadd_vf_f32m1_m_rm(vbool32_t mask, vfloat32m1_t op1, float32_t op2,
+			 size_t vl) {
+  return __riscv_vfadd_vf_f32m1_m_rm(mask, op1, op2, 7, vl);
+}
+
+/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 4 } } */
+/* { dg-final { scan-assembler-not {fsrm\s+[ax][0-9]+,\s*[ax][0-9]+} } } */
-- 
2.34.1

Re: [PATCH v5] RISC-V: Fix one bug for floating-point static frm

[Robin Dapp]

Hi Pan,

thanks,  I think that works for me as I'm expecting these
parts to change a bit anyway in the near future.

There is no functional change to the last revision that
Kito already OK'ed so I think you can go ahead.

Regards
 Robin

RE: [PATCH v5] RISC-V: Fix one bug for floating-point static frm

[Li, Pan2]

Committed, thanks Robin and Kito.

Pan

-----Original Message-----
From: Robin Dapp <rdapp.gcc@gmail.com> 
Sent: Thursday, July 6, 2023 11:30 PM
To: Li, Pan2 <pan2.li@intel.com>; gcc-patches@gcc.gnu.org
Cc: rdapp.gcc@gmail.com; juzhe.zhong@rivai.ai; jeffreyalaw@gmail.com; Wang, Yanzhang <yanzhang.wang@intel.com>; kito.cheng@gmail.com; Robin Dapp <rdapp@ventanamicro.com>
Subject: Re: [PATCH v5] RISC-V: Fix one bug for floating-point static frm

Hi Pan,

thanks,  I think that works for me as I'm expecting these
parts to change a bit anyway in the near future.

There is no functional change to the last revision that
Kito already OK'ed so I think you can go ahead.

Regards
 Robin