* [PATCH 0/5] RISC-V: Add Types to Untyped Instructions
@ 2023-09-06 17:50 Edwin Lu
2023-09-06 17:50 ` [PATCH 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
` (4 more replies)
0 siblings, 5 replies; 20+ messages in thread
From: Edwin Lu @ 2023-09-06 17:50 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This series adds types to the remaining untyped instructions.
Related Discussion:
https://inbox.sourceware.org/gcc-patches/12fb5088-3f28-0a69-de1e-f387371a5eb2@gmail.com/
Also enables assert which checks to make sure every instruction has a type
All patches were tested with rv32/rv64 linux/newlib multilib
Additional extensions tested:
gcv
gc_zba_zbb_zbc_zbs
Edwin Lu (5):
RISC-V: Update Types for Vector Instructions
RISC-V: Add Types for Un-Typed zc Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Add Types to Un-Typed Zicond Instructions
RISC-V: Remove Assert Protecting Types
gcc/config/riscv/autovec-opt.md | 42 ++++++++-----
gcc/config/riscv/autovec.md | 28 ++++++---
gcc/config/riscv/riscv.cc | 2 -
gcc/config/riscv/riscv.md | 9 ++-
gcc/config/riscv/zc.md | 102 ++++++++++++++++----------------
gcc/config/riscv/zicond.md | 8 +--
6 files changed, 110 insertions(+), 81 deletions(-)
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 1/5] RISC-V: Update Types for Vector Instructions
2023-09-06 17:50 [PATCH 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
@ 2023-09-06 17:50 ` Edwin Lu
2023-09-06 23:23 ` Kito Cheng
2023-09-06 17:50 ` [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
` (3 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Edwin Lu @ 2023-09-06 17:50 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This patch adds types to vector instructions that were added after or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
gcc/ChangeLog:
* config/riscv/autovec-opt.md: Update types
* config/riscv/autovec.md: likewise
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
gcc/config/riscv/autovec-opt.md | 42 ++++++++++++++++++++++-----------
gcc/config/riscv/autovec.md | 28 +++++++++++++++-------
2 files changed, 47 insertions(+), 23 deletions(-)
diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md
index 1ca5ce97193..6cc1a01629c 100644
--- a/gcc/config/riscv/autovec-opt.md
+++ b/gcc/config/riscv/autovec-opt.md
@@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs<mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode),
const0_rtx));
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine vlmax neg and UNSPEC_VCOPYSIGN
(define_insn_and_split "*copysign<mode>_neg"
@@ -746,7 +747,8 @@ (define_insn_and_split "*copysign<mode>_neg"
riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (<MODE>mode),
riscv_vector::BINARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf2) and vcond_mask
(define_insn_and_split "*cond_<optab><v_double_trunc><mode>"
@@ -765,7 +767,8 @@ (define_insn_and_split "*cond_<optab><v_double_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf4) and vcond_mask
(define_insn_and_split "*cond_<optab><v_quad_trunc><mode>"
@@ -784,7 +787,8 @@ (define_insn_and_split "*cond_<optab><v_quad_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine sign_extend/zero_extend(vf8) and vcond_mask
(define_insn_and_split "*cond_<optab><v_oct_trunc><mode>"
@@ -803,7 +807,8 @@ (define_insn_and_split "*cond_<optab><v_oct_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine trunc(vf2) + vcond_mask
(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
@@ -823,7 +828,8 @@ (define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask
(define_insn_and_split "*cond_extend<v_double_trunc><mode>"
@@ -842,7 +848,8 @@ (define_insn_and_split "*cond_extend<v_double_trunc><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine FP trunc(vf2) + vcond_mask
(define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
@@ -862,7 +869,8 @@ (define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(FP->INT) + vcond_mask
(define_insn_and_split "*cond_<optab><mode><vconvert>"
@@ -882,7 +890,8 @@ (define_insn_and_split "*cond_<optab><mode><vconvert>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(INT->FP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
@@ -902,7 +911,8 @@ (define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(FP->2xINT) + vcond_mask
(define_insn_and_split "*cond_<optab><vnconvert><mode>"
@@ -922,7 +932,8 @@ (define_insn_and_split "*cond_<optab><vnconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(INT->2xFP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
@@ -942,7 +953,8 @@ (define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(2xFP->INT) + vcond_mask
(define_insn_and_split "*cond_<optab><mode><vnconvert>"
@@ -962,7 +974,8 @@ (define_insn_and_split "*cond_<optab><mode><vnconvert>"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; Combine convert(2xINT->FP) + vcond_mask
(define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2"
@@ -982,4 +995,5 @@ (define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2"
gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
riscv_vector::expand_cond_len_unop (icode, ops);
DONE;
-})
+}
+[(set_attr "type" "vector")])
diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
index 0f9d1fe2c8e..047a66b238f 100644
--- a/gcc/config/riscv/autovec.md
+++ b/gcc/config/riscv/autovec.md
@@ -558,6 +558,7 @@ (define_insn_and_split "@vcond_mask_<mode><vm>"
riscv_vector::MERGE_OP, operands);
DONE;
}
+ [(set_attr "type" "vector")]
)
;; -------------------------------------------------------------------------
@@ -645,7 +646,8 @@ (define_insn_and_split "<optab><v_quad_trunc><mode>2"
insn_code icode = code_for_pred_vf4 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vext")])
(define_insn_and_split "<optab><v_oct_trunc><mode>2"
[(set (match_operand:VOEXTI 0 "register_operand")
@@ -659,7 +661,8 @@ (define_insn_and_split "<optab><v_oct_trunc><mode>2"
insn_code icode = code_for_pred_vf8 (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vext")])
;; -------------------------------------------------------------------------
;; ---- [INT] Truncation
@@ -815,7 +818,8 @@ (define_insn_and_split "<optab><mode><vconvert>2"
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfcvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Conversions
@@ -837,7 +841,8 @@ (define_insn_and_split "<float_cvt><vconvert><mode>2"
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfcvtitof")])
;; =========================================================================
;; == Widening/narrowing Conversions
@@ -862,7 +867,8 @@ (define_insn_and_split "<optab><vnconvert><mode>2"
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwcvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Widening Conversions
@@ -883,7 +889,8 @@ (define_insn_and_split "<float_cvt><vnconvert><mode>2"
insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfwcvtitof")])
;; -------------------------------------------------------------------------
;; ---- [INT<-FP] Narrowing Conversions
@@ -904,7 +911,8 @@ (define_insn_and_split "<optab><mode><vnconvert>2"
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vfncvtftoi")])
;; -------------------------------------------------------------------------
;; ---- [FP<-INT] Narrowing Conversions
@@ -925,7 +933,8 @@ (define_insn_and_split "<float_cvt><mode><vnconvert>2"
insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN, operands);
DONE;
-})
+}
+[(set_attr "type" "vfncvtitof")])
;; =========================================================================
;; == Unary arithmetic
@@ -986,7 +995,8 @@ (define_insn_and_split "<optab><mode>2"
insn_code icode = code_for_pred (<CODE>, <MODE>mode);
riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
DONE;
-})
+}
+[(set_attr "type" "vector")])
;; -------------------------------------------------------------------------------
;; - [FP] Square root
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions
2023-09-06 17:50 [PATCH 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
2023-09-06 17:50 ` [PATCH 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
@ 2023-09-06 17:50 ` Edwin Lu
2023-09-06 23:33 ` Kito Cheng
2023-09-06 17:50 ` [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions Edwin Lu
` (2 subsequent siblings)
4 siblings, 1 reply; 20+ messages in thread
From: Edwin Lu @ 2023-09-06 17:50 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This patch adds types to the untyped zc instructions. Creates a new
type "csr" for these instructions for now.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "csr" type
* config/riscv/zc.md: Update types
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
gcc/config/riscv/riscv.md | 3 +-
gcc/config/riscv/zc.md | 102 +++++++++++++++++++-------------------
2 files changed, 54 insertions(+), 51 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index d80b6938f84..6684ad89cff 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -312,6 +312,7 @@ (define_attr "ext_enabled" "no,yes"
;; condmove conditional moves
;; cbo cache block instructions
;; crypto cryptography instructions
+;; csr code size reduction instructions
;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
;; rdvlenb vector byte length vlenb csrr read
;; rdvl vector length vl csrr read
@@ -421,7 +422,7 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
- atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
+ atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
index 77b28adde95..86f1afd66cb 100644
--- a/gcc/config/riscv/zc.md
+++ b/gcc/config/riscv/zc.md
@@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_<mode>"
(const_int <slot0_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_<mode>"
(const_int <slot1_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_<mode>"
(const_int <slot2_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s1}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_<mode>"
(const_int <slot3_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s2}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_<mode>"
(const_int <slot4_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s3}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_<mode>"
(const_int <slot5_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s4}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_<mode>"
(const_int <slot6_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s5}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_<mode>"
(const_int <slot7_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s6}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_<mode>"
(const_int <slot8_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s7}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_<mode>"
(const_int <slot9_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s8}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_<mode>"
(const_int <slot10_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s9}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_pop_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_<mode>"
(const_int <slot12_offset>))))]
"TARGET_ZCMP"
"cm.pop {ra, s0-s11}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_ra_<mode>"
[(set (reg:X SP_REGNUM)
@@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -378,7 +378,7 @@ (define_insn "@gpr_multi_popret_up_to_s0_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -397,7 +397,7 @@ (define_insn "@gpr_multi_popret_up_to_s1_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s1}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -419,7 +419,7 @@ (define_insn "@gpr_multi_popret_up_to_s2_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s2}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -444,7 +444,7 @@ (define_insn "@gpr_multi_popret_up_to_s3_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s3}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -472,7 +472,7 @@ (define_insn "@gpr_multi_popret_up_to_s4_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s4}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -503,7 +503,7 @@ (define_insn "@gpr_multi_popret_up_to_s5_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s5}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -537,7 +537,7 @@ (define_insn "@gpr_multi_popret_up_to_s6_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s6}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -574,7 +574,7 @@ (define_insn "@gpr_multi_popret_up_to_s7_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s7}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -614,7 +614,7 @@ (define_insn "@gpr_multi_popret_up_to_s8_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s8}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -657,7 +657,7 @@ (define_insn "@gpr_multi_popret_up_to_s9_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s9}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popret_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -706,7 +706,7 @@ (define_insn "@gpr_multi_popret_up_to_s11_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popret {ra, s0-s11}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
[(set (reg:X SP_REGNUM)
@@ -722,7 +722,7 @@ (define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
[(set (reg:X SP_REGNUM)
@@ -741,7 +741,7 @@ (define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
[(set (reg:X SP_REGNUM)
@@ -763,7 +763,7 @@ (define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s1}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
[(set (reg:X SP_REGNUM)
@@ -788,7 +788,7 @@ (define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s2}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
[(set (reg:X SP_REGNUM)
@@ -816,7 +816,7 @@ (define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s3}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
[(set (reg:X SP_REGNUM)
@@ -847,7 +847,7 @@ (define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s4}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
[(set (reg:X SP_REGNUM)
@@ -881,7 +881,7 @@ (define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s5}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
[(set (reg:X SP_REGNUM)
@@ -918,7 +918,7 @@ (define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s6}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
[(set (reg:X SP_REGNUM)
@@ -958,7 +958,7 @@ (define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s7}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1001,7 +1001,7 @@ (define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s8}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1047,7 +1047,7 @@ (define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s9}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
[(set (reg:X SP_REGNUM)
@@ -1099,7 +1099,7 @@ (define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
(use (reg:SI RETURN_ADDR_REGNUM))]
"TARGET_ZCMP"
"cm.popretz {ra, s0-s11}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_ra_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1110,7 +1110,7 @@ (define_insn "@gpr_multi_push_up_to_ra_<mode>"
(match_operand 0 "stack_push_up_to_ra_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s0_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1124,7 +1124,7 @@ (define_insn "@gpr_multi_push_up_to_s0_<mode>"
(match_operand 0 "stack_push_up_to_s0_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s1_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1141,7 +1141,7 @@ (define_insn "@gpr_multi_push_up_to_s1_<mode>"
(match_operand 0 "stack_push_up_to_s1_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s1}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s2_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1161,7 +1161,7 @@ (define_insn "@gpr_multi_push_up_to_s2_<mode>"
(match_operand 0 "stack_push_up_to_s2_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s2}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s3_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1184,7 +1184,7 @@ (define_insn "@gpr_multi_push_up_to_s3_<mode>"
(match_operand 0 "stack_push_up_to_s3_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s3}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s4_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1210,7 +1210,7 @@ (define_insn "@gpr_multi_push_up_to_s4_<mode>"
(match_operand 0 "stack_push_up_to_s4_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s4}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s5_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1239,7 +1239,7 @@ (define_insn "@gpr_multi_push_up_to_s5_<mode>"
(match_operand 0 "stack_push_up_to_s5_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s5}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s6_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1271,7 +1271,7 @@ (define_insn "@gpr_multi_push_up_to_s6_<mode>"
(match_operand 0 "stack_push_up_to_s6_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s6}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s7_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1306,7 +1306,7 @@ (define_insn "@gpr_multi_push_up_to_s7_<mode>"
(match_operand 0 "stack_push_up_to_s7_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s7}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s8_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1344,7 +1344,7 @@ (define_insn "@gpr_multi_push_up_to_s8_<mode>"
(match_operand 0 "stack_push_up_to_s8_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s8}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s9_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1385,7 +1385,7 @@ (define_insn "@gpr_multi_push_up_to_s9_<mode>"
(match_operand 0 "stack_push_up_to_s9_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s9}, %0"
-)
+[(set_attr "type" "csr")])
(define_insn "@gpr_multi_push_up_to_s11_<mode>"
[(set (mem:X (plus:X (reg:X SP_REGNUM)
@@ -1432,7 +1432,7 @@ (define_insn "@gpr_multi_push_up_to_s11_<mode>"
(match_operand 0 "stack_push_up_to_s11_operand" "I")))]
"TARGET_ZCMP"
"cm.push {ra, s0-s11}, %0"
-)
+[(set_attr "type" "csr")])
;; ZCMP mv
(define_insn "*mva01s<X:mode>"
@@ -1443,7 +1443,8 @@ (define_insn "*mva01s<X:mode>"
"TARGET_ZCMP
&& (REGNO (operands[2]) != REGNO (operands[0]))"
{ return (REGNO (operands[0]) == A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; }
- [(set_attr "mode" "<X:MODE>")])
+ [(set_attr "mode" "<X:MODE>")
+ (set_attr "type" "csr")])
(define_insn "*mvsa01<X:mode>"
[(set (match_operand:X 0 "zcmp_mv_sreg_operand" "=r")
@@ -1454,4 +1455,5 @@ (define_insn "*mvsa01<X:mode>"
&& (REGNO (operands[0]) != REGNO (operands[2]))
&& (REGNO (operands[1]) != REGNO (operands[3]))"
{ return (REGNO (operands[1]) == A0_REGNUM)?"cm.mvsa01\t%0,%2":"cm.mvsa01\t%2,%0"; }
- [(set_attr "mode" "<X:MODE>")])
+ [(set_attr "mode" "<X:MODE>")
+ (set_attr "type" "csr")])
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions
2023-09-06 17:50 [PATCH 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
2023-09-06 17:50 ` [PATCH 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
2023-09-06 17:50 ` [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
@ 2023-09-06 17:50 ` Edwin Lu
2023-09-06 23:22 ` Kito Cheng
2023-09-07 0:42 ` Tsukasa OI
2023-09-06 17:50 ` [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions Edwin Lu
2023-09-06 17:50 ` [PATCH 5/5] RISC-V: Remove Assert Protecting Types Edwin Lu
4 siblings, 2 replies; 20+ messages in thread
From: Edwin Lu @ 2023-09-06 17:50 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This patch creates a new "zicond" type and updates all zicond instructions
with that type.
gcc/ChangeLog:
* config/riscv/riscv.md: Add "zicond" type
* config/riscv/zicond.md: Update types
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
gcc/config/riscv/riscv.md | 5 +++--
gcc/config/riscv/zicond.md | 8 ++++----
2 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 6684ad89cff..c329f55db43 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes"
;; cbo cache block instructions
;; crypto cryptography instructions
;; csr code size reduction instructions
+;; zicond zicond instructions
;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
;; rdvlenb vector byte length vlenb csrr read
;; rdvl vector length vl csrr read
@@ -422,8 +423,8 @@ (define_attr "type"
mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
- atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
- vlde,vste,vldm,vstm,vlds,vsts,
+ atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,
+ vsetvl, vlde,vste,vldm,vstm,vlds,vsts,
vldux,vldox,vstux,vstox,vldff,vldr,vstr,
vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
index 1721e1011ea..0269bd14399 100644
--- a/gcc/config/riscv/zicond.md
+++ b/gcc/config/riscv/zicond.md
@@ -30,7 +30,7 @@ (define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
(const_int 0)))]
"TARGET_ZICOND"
"czero.<eqz>\t%0,%2,%1"
-)
+[(set_attr "type" "zicond")])
(define_insn "*czero.<nez>.<GPR:mode><X:mode>"
[(set (match_operand:GPR 0 "register_operand" "=r")
@@ -40,7 +40,7 @@ (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
(match_operand:GPR 2 "register_operand" "r")))]
"TARGET_ZICOND"
"czero.<nez>\t%0,%2,%1"
-)
+[(set_attr "type" "zicond")])
;; Special optimization under eq/ne in primitive semantics
(define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
@@ -51,7 +51,7 @@ (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
(match_operand:GPR 3 "register_operand" "r")))]
"TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
"czero.eqz\t%0,%3,%1"
-)
+[(set_attr "type" "zicond")])
(define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
[(set (match_operand:GPR 0 "register_operand" "=r")
@@ -61,7 +61,7 @@ (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
(match_operand:GPR 3 "register_operand" "1")))]
"TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
"czero.eqz\t%0,%2,%1"
-)
+[(set_attr "type" "zicond")])
;; Combine creates this form in some cases (particularly the coremark
;; CRC loop.
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions
2023-09-06 17:50 [PATCH 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
` (2 preceding siblings ...)
2023-09-06 17:50 ` [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions Edwin Lu
@ 2023-09-06 17:50 ` Edwin Lu
2023-09-06 23:23 ` Kito Cheng
2023-09-06 17:50 ` [PATCH 5/5] RISC-V: Remove Assert Protecting Types Edwin Lu
4 siblings, 1 reply; 20+ messages in thread
From: Edwin Lu @ 2023-09-06 17:50 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This patch adds types to riscv instructions that were added or were
missed by the original patch
https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
gcc/ChangeLog:
* config/riscv/riscv.md: Update types
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
gcc/config/riscv/riscv.md | 3 +++
1 file changed, 3 insertions(+)
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index c329f55db43..c1cecd27815 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmv.x.w\t%0,%1"
[(set_attr "move_type" "fmove")
+ (set_attr "type" "fmove")
(set_attr "mode" "DF")])
@@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmvh.x.d\t%0,%1"
[(set_attr "move_type" "fmove")
+ (set_attr "type" "fmove")
(set_attr "mode" "DF")])
(define_insn "movdfsisi3_rv32"
@@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
"TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
"fmvp.d.x\t%0,%2,%1"
[(set_attr "move_type" "fmove")
+ (set_attr "type" "fmove")
(set_attr "mode" "DF")])
(define_split
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 5/5] RISC-V: Remove Assert Protecting Types
2023-09-06 17:50 [PATCH 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
` (3 preceding siblings ...)
2023-09-06 17:50 ` [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions Edwin Lu
@ 2023-09-06 17:50 ` Edwin Lu
2023-09-07 13:19 ` Jeff Law
4 siblings, 1 reply; 20+ messages in thread
From: Edwin Lu @ 2023-09-06 17:50 UTC (permalink / raw)
To: gcc-patches; +Cc: gnu-toolchain, Edwin Lu
This patch turns on the assert which ensures every instruction has type
that is not TYPE_UNKNOWN.
gcc/ChangeLog:
* config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
---
gcc/config/riscv/riscv.cc | 2 --
1 file changed, 2 deletions(-)
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ef63079de8e..f0576351cda 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -7330,11 +7330,9 @@ riscv_sched_variable_issue (FILE *, int, rtx_insn *insn, int more)
if (get_attr_type (insn) == TYPE_GHOST)
return 0;
-#if 0
/* If we ever encounter an insn with an unknown type, trip
an assert so we can find and fix this problem. */
gcc_assert (get_attr_type (insn) != TYPE_UNKNOWN);
-#endif
return more - 1;
}
--
2.34.1
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions
2023-09-06 17:50 ` [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions Edwin Lu
@ 2023-09-06 23:22 ` Kito Cheng
2023-09-07 0:42 ` Tsukasa OI
1 sibling, 0 replies; 20+ messages in thread
From: Kito Cheng @ 2023-09-06 23:22 UTC (permalink / raw)
To: Edwin Lu; +Cc: GCC Patches, gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 3504 bytes --]
LGTM
Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:53 寫道：
> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "zicond" type
> * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> ---
> gcc/config/riscv/riscv.md | 5 +++--
> gcc/config/riscv/zicond.md | 8 ++++----
> 2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 6684ad89cff..c329f55db43 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes"
> ;; cbo cache block instructions
> ;; crypto cryptography instructions
> ;; csr code size reduction instructions
> +;; zicond zicond instructions
> ;; Classification of RVV instructions which will be added to each RVV .md
> pattern and used by scheduler.
> ;; rdvlenb vector byte length vlenb csrr read
> ;; rdvl vector length vl csrr read
> @@ -422,8 +423,8 @@ (define_attr "type"
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
> rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
> - atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> - vlde,vste,vldm,vstm,vlds,vsts,
> + atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,
> + vsetvl, vlde,vste,vldm,vstm,vlds,vsts,
> vldux,vldox,vstux,vstox,vldff,vldr,vstr,
>
> vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
> vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
> diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
> index 1721e1011ea..0269bd14399 100644
> --- a/gcc/config/riscv/zicond.md
> +++ b/gcc/config/riscv/zicond.md
> @@ -30,7 +30,7 @@ (define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
> (const_int 0)))]
> "TARGET_ZICOND"
> "czero.<eqz>\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
> (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
> [(set (match_operand:GPR 0 "register_operand" "=r")
> @@ -40,7 +40,7 @@ (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
> (match_operand:GPR 2 "register_operand"
> "r")))]
> "TARGET_ZICOND"
> "czero.<nez>\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
> ;; Special optimization under eq/ne in primitive semantics
> (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
> @@ -51,7 +51,7 @@ (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
> (match_operand:GPR 3 "register_operand" "r")))]
> "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
> "czero.eqz\t%0,%3,%1"
> -)
> +[(set_attr "type" "zicond")])
>
> (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
> [(set (match_operand:GPR 0 "register_operand" "=r")
> @@ -61,7 +61,7 @@ (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
> (match_operand:GPR 3 "register_operand" "1")))]
> "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
> "czero.eqz\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
> ;; Combine creates this form in some cases (particularly the coremark
> ;; CRC loop.
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions
2023-09-06 17:50 ` [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions Edwin Lu
@ 2023-09-06 23:23 ` Kito Cheng
2023-09-11 17:48 ` [PATCH 4/5][Committed] " Edwin Lu
0 siblings, 1 reply; 20+ messages in thread
From: Kito Cheng @ 2023-09-06 23:23 UTC (permalink / raw)
To: Edwin Lu; +Cc: GCC Patches, gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 1457 bytes --]
LGTM
Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:52 寫道：
> This patch adds types to riscv instructions that were added or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Update types
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> ---
> gcc/config/riscv/riscv.md | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index c329f55db43..c1cecd27815 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
> "fmv.x.w\t%0,%1"
> [(set_attr "move_type" "fmove")
> + (set_attr "type" "fmove")
> (set_attr "mode" "DF")])
>
>
> @@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
> "fmvh.x.d\t%0,%1"
> [(set_attr "move_type" "fmove")
> + (set_attr "type" "fmove")
> (set_attr "mode" "DF")])
>
> (define_insn "movdfsisi3_rv32"
> @@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
> "fmvp.d.x\t%0,%2,%1"
> [(set_attr "move_type" "fmove")
> + (set_attr "type" "fmove")
> (set_attr "mode" "DF")])
>
> (define_split
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/5] RISC-V: Update Types for Vector Instructions
2023-09-06 17:50 ` [PATCH 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
@ 2023-09-06 23:23 ` Kito Cheng
2023-09-07 17:26 ` Edwin Lu
0 siblings, 1 reply; 20+ messages in thread
From: Kito Cheng @ 2023-09-06 23:23 UTC (permalink / raw)
To: Edwin Lu; +Cc: GCC Patches, gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 10257 bytes --]
LGTM
Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to vector instructions that were added after or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Update types
> * config/riscv/autovec.md: likewise
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> ---
> gcc/config/riscv/autovec-opt.md | 42 ++++++++++++++++++++++-----------
> gcc/config/riscv/autovec.md | 28 +++++++++++++++-------
> 2 files changed, 47 insertions(+), 23 deletions(-)
>
> diff --git a/gcc/config/riscv/autovec-opt.md
> b/gcc/config/riscv/autovec-opt.md
> index 1ca5ce97193..6cc1a01629c 100644
> --- a/gcc/config/riscv/autovec-opt.md
> +++ b/gcc/config/riscv/autovec-opt.md
> @@ -728,7 +728,8 @@ (define_insn_and_split "*cond_abs<mode>"
> gen_int_mode (GET_MODE_NUNITS
> (<MODE>mode), Pmode),
> const0_rtx));
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine vlmax neg and UNSPEC_VCOPYSIGN
> (define_insn_and_split "*copysign<mode>_neg"
> @@ -746,7 +747,8 @@ (define_insn_and_split "*copysign<mode>_neg"
> riscv_vector::emit_vlmax_insn (code_for_pred_ncopysign (<MODE>mode),
> riscv_vector::BINARY_OP, operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine sign_extend/zero_extend(vf2) and vcond_mask
> (define_insn_and_split "*cond_<optab><v_double_trunc><mode>"
> @@ -765,7 +767,8 @@ (define_insn_and_split
> "*cond_<optab><v_double_trunc><mode>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine sign_extend/zero_extend(vf4) and vcond_mask
> (define_insn_and_split "*cond_<optab><v_quad_trunc><mode>"
> @@ -784,7 +787,8 @@ (define_insn_and_split
> "*cond_<optab><v_quad_trunc><mode>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine sign_extend/zero_extend(vf8) and vcond_mask
> (define_insn_and_split "*cond_<optab><v_oct_trunc><mode>"
> @@ -803,7 +807,8 @@ (define_insn_and_split
> "*cond_<optab><v_oct_trunc><mode>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine trunc(vf2) + vcond_mask
> (define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
> @@ -823,7 +828,8 @@ (define_insn_and_split
> "*cond_trunc<mode><v_double_trunc>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine FP sign_extend/zero_extend(vf2) and vcond_mask
> (define_insn_and_split "*cond_extend<v_double_trunc><mode>"
> @@ -842,7 +848,8 @@ (define_insn_and_split
> "*cond_extend<v_double_trunc><mode>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine FP trunc(vf2) + vcond_mask
> (define_insn_and_split "*cond_trunc<mode><v_double_trunc>"
> @@ -862,7 +869,8 @@ (define_insn_and_split
> "*cond_trunc<mode><v_double_trunc>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine convert(FP->INT) + vcond_mask
> (define_insn_and_split "*cond_<optab><mode><vconvert>"
> @@ -882,7 +890,8 @@ (define_insn_and_split "*cond_<optab><mode><vconvert>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine convert(INT->FP) + vcond_mask
> (define_insn_and_split "*cond_<float_cvt><vconvert><mode>"
> @@ -902,7 +911,8 @@ (define_insn_and_split
> "*cond_<float_cvt><vconvert><mode>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine convert(FP->2xINT) + vcond_mask
> (define_insn_and_split "*cond_<optab><vnconvert><mode>"
> @@ -922,7 +932,8 @@ (define_insn_and_split "*cond_<optab><vnconvert><mode>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine convert(INT->2xFP) + vcond_mask
> (define_insn_and_split "*cond_<float_cvt><vnconvert><mode>"
> @@ -942,7 +953,8 @@ (define_insn_and_split
> "*cond_<float_cvt><vnconvert><mode>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine convert(2xFP->INT) + vcond_mask
> (define_insn_and_split "*cond_<optab><mode><vnconvert>"
> @@ -962,7 +974,8 @@ (define_insn_and_split "*cond_<optab><mode><vnconvert>"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;; Combine convert(2xINT->FP) + vcond_mask
> (define_insn_and_split "*cond_<float_cvt><mode><vnconvert>2"
> @@ -982,4 +995,5 @@ (define_insn_and_split
> "*cond_<float_cvt><mode><vnconvert>2"
> gen_int_mode (GET_MODE_NUNITS (<MODE>mode), Pmode)};
> riscv_vector::expand_cond_len_unop (icode, ops);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
> diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md
> index 0f9d1fe2c8e..047a66b238f 100644
> --- a/gcc/config/riscv/autovec.md
> +++ b/gcc/config/riscv/autovec.md
> @@ -558,6 +558,7 @@ (define_insn_and_split "@vcond_mask_<mode><vm>"
> riscv_vector::MERGE_OP, operands);
> DONE;
> }
> + [(set_attr "type" "vector")]
> )
>
> ;;
> -------------------------------------------------------------------------
> @@ -645,7 +646,8 @@ (define_insn_and_split "<optab><v_quad_trunc><mode>2"
> insn_code icode = code_for_pred_vf4 (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vext")])
>
> (define_insn_and_split "<optab><v_oct_trunc><mode>2"
> [(set (match_operand:VOEXTI 0 "register_operand")
> @@ -659,7 +661,8 @@ (define_insn_and_split "<optab><v_oct_trunc><mode>2"
> insn_code icode = code_for_pred_vf8 (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vext")])
>
> ;;
> -------------------------------------------------------------------------
> ;; ---- [INT] Truncation
> @@ -815,7 +818,8 @@ (define_insn_and_split "<optab><mode><vconvert>2"
> insn_code icode = code_for_pred (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vfcvtftoi")])
>
> ;;
> -------------------------------------------------------------------------
> ;; ---- [FP<-INT] Conversions
> @@ -837,7 +841,8 @@ (define_insn_and_split "<float_cvt><vconvert><mode>2"
> insn_code icode = code_for_pred (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN,
> operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vfcvtitof")])
>
> ;;
> =========================================================================
> ;; == Widening/narrowing Conversions
> @@ -862,7 +867,8 @@ (define_insn_and_split "<optab><vnconvert><mode>2"
> insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vfwcvtftoi")])
>
> ;;
> -------------------------------------------------------------------------
> ;; ---- [FP<-INT] Widening Conversions
> @@ -883,7 +889,8 @@ (define_insn_and_split "<float_cvt><vnconvert><mode>2"
> insn_code icode = code_for_pred_widen (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vfwcvtitof")])
>
> ;;
> -------------------------------------------------------------------------
> ;; ---- [INT<-FP] Narrowing Conversions
> @@ -904,7 +911,8 @@ (define_insn_and_split "<optab><mode><vnconvert>2"
> insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vfncvtftoi")])
>
> ;;
> -------------------------------------------------------------------------
> ;; ---- [FP<-INT] Narrowing Conversions
> @@ -925,7 +933,8 @@ (define_insn_and_split "<float_cvt><mode><vnconvert>2"
> insn_code icode = code_for_pred_narrow (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP_FRM_DYN,
> operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vfncvtitof")])
>
> ;;
> =========================================================================
> ;; == Unary arithmetic
> @@ -986,7 +995,8 @@ (define_insn_and_split "<optab><mode>2"
> insn_code icode = code_for_pred (<CODE>, <MODE>mode);
> riscv_vector::emit_vlmax_insn (icode, riscv_vector::UNARY_OP, operands);
> DONE;
> -})
> +}
> +[(set_attr "type" "vector")])
>
> ;;
> -------------------------------------------------------------------------------
> ;; - [FP] Square root
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions
2023-09-06 17:50 ` [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
@ 2023-09-06 23:33 ` Kito Cheng
2023-09-07 17:29 ` Edwin Lu
0 siblings, 1 reply; 20+ messages in thread
From: Kito Cheng @ 2023-09-06 23:33 UTC (permalink / raw)
To: Edwin Lu; +Cc: GCC Patches, gnu-toolchain
[-- Attachment #1: Type: text/plain, Size: 17518 bytes --]
csr is kind of confusing, I would suggest something like `pushpop` and
`mvpair`.
Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:51 寫道：
> This patch adds types to the untyped zc instructions. Creates a new
> type "csr" for these instructions for now.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "csr" type
> * config/riscv/zc.md: Update types
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> ---
> gcc/config/riscv/riscv.md | 3 +-
> gcc/config/riscv/zc.md | 102 +++++++++++++++++++-------------------
> 2 files changed, 54 insertions(+), 51 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index d80b6938f84..6684ad89cff 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -312,6 +312,7 @@ (define_attr "ext_enabled" "no,yes"
> ;; condmove conditional moves
> ;; cbo cache block instructions
> ;; crypto cryptography instructions
> +;; csr code size reduction instructions
> ;; Classification of RVV instructions which will be added to each RVV .md
> pattern and used by scheduler.
> ;; rdvlenb vector byte length vlenb csrr read
> ;; rdvl vector length vl csrr read
> @@ -421,7 +422,7 @@ (define_attr "type"
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
> rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
> - atomic,condmove,cbo,crypto,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> + atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> vlde,vste,vldm,vstm,vlds,vsts,
> vldux,vldox,vstux,vstox,vldff,vldr,vstr,
>
> vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
> diff --git a/gcc/config/riscv/zc.md b/gcc/config/riscv/zc.md
> index 77b28adde95..86f1afd66cb 100644
> --- a/gcc/config/riscv/zc.md
> +++ b/gcc/config/riscv/zc.md
> @@ -27,7 +27,7 @@ (define_insn "@gpr_multi_pop_up_to_ra_<mode>"
> (const_int <slot0_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s0_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -41,7 +41,7 @@ (define_insn "@gpr_multi_pop_up_to_s0_<mode>"
> (const_int <slot1_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s1_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -58,7 +58,7 @@ (define_insn "@gpr_multi_pop_up_to_s1_<mode>"
> (const_int <slot2_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s1}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s2_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -78,7 +78,7 @@ (define_insn "@gpr_multi_pop_up_to_s2_<mode>"
> (const_int <slot3_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s2}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s3_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -101,7 +101,7 @@ (define_insn "@gpr_multi_pop_up_to_s3_<mode>"
> (const_int <slot4_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s3}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s4_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -127,7 +127,7 @@ (define_insn "@gpr_multi_pop_up_to_s4_<mode>"
> (const_int <slot5_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s4}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s5_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -156,7 +156,7 @@ (define_insn "@gpr_multi_pop_up_to_s5_<mode>"
> (const_int <slot6_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s5}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s6_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -188,7 +188,7 @@ (define_insn "@gpr_multi_pop_up_to_s6_<mode>"
> (const_int <slot7_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s6}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s7_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -223,7 +223,7 @@ (define_insn "@gpr_multi_pop_up_to_s7_<mode>"
> (const_int <slot8_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s7}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s8_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -261,7 +261,7 @@ (define_insn "@gpr_multi_pop_up_to_s8_<mode>"
> (const_int <slot9_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s8}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s9_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -302,7 +302,7 @@ (define_insn "@gpr_multi_pop_up_to_s9_<mode>"
> (const_int <slot10_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s9}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_pop_up_to_s11_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -349,7 +349,7 @@ (define_insn "@gpr_multi_pop_up_to_s11_<mode>"
> (const_int <slot12_offset>))))]
> "TARGET_ZCMP"
> "cm.pop {ra, s0-s11}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_ra_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -362,7 +362,7 @@ (define_insn "@gpr_multi_popret_up_to_ra_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s0_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -378,7 +378,7 @@ (define_insn "@gpr_multi_popret_up_to_s0_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s1_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -397,7 +397,7 @@ (define_insn "@gpr_multi_popret_up_to_s1_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s1}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s2_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -419,7 +419,7 @@ (define_insn "@gpr_multi_popret_up_to_s2_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s2}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s3_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -444,7 +444,7 @@ (define_insn "@gpr_multi_popret_up_to_s3_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s3}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s4_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -472,7 +472,7 @@ (define_insn "@gpr_multi_popret_up_to_s4_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s4}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s5_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -503,7 +503,7 @@ (define_insn "@gpr_multi_popret_up_to_s5_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s5}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s6_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -537,7 +537,7 @@ (define_insn "@gpr_multi_popret_up_to_s6_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s6}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s7_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -574,7 +574,7 @@ (define_insn "@gpr_multi_popret_up_to_s7_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s7}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s8_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -614,7 +614,7 @@ (define_insn "@gpr_multi_popret_up_to_s8_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s8}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s9_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -657,7 +657,7 @@ (define_insn "@gpr_multi_popret_up_to_s9_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s9}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popret_up_to_s11_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -706,7 +706,7 @@ (define_insn "@gpr_multi_popret_up_to_s11_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popret {ra, s0-s11}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -722,7 +722,7 @@ (define_insn "@gpr_multi_popretz_up_to_ra_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -741,7 +741,7 @@ (define_insn "@gpr_multi_popretz_up_to_s0_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -763,7 +763,7 @@ (define_insn "@gpr_multi_popretz_up_to_s1_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s1}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -788,7 +788,7 @@ (define_insn "@gpr_multi_popretz_up_to_s2_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s2}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -816,7 +816,7 @@ (define_insn "@gpr_multi_popretz_up_to_s3_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s3}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -847,7 +847,7 @@ (define_insn "@gpr_multi_popretz_up_to_s4_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s4}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -881,7 +881,7 @@ (define_insn "@gpr_multi_popretz_up_to_s5_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s5}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -918,7 +918,7 @@ (define_insn "@gpr_multi_popretz_up_to_s6_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s6}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -958,7 +958,7 @@ (define_insn "@gpr_multi_popretz_up_to_s7_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s7}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -1001,7 +1001,7 @@ (define_insn "@gpr_multi_popretz_up_to_s8_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s8}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -1047,7 +1047,7 @@ (define_insn "@gpr_multi_popretz_up_to_s9_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s9}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
> [(set (reg:X SP_REGNUM)
> @@ -1099,7 +1099,7 @@ (define_insn "@gpr_multi_popretz_up_to_s11_<mode>"
> (use (reg:SI RETURN_ADDR_REGNUM))]
> "TARGET_ZCMP"
> "cm.popretz {ra, s0-s11}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_ra_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1110,7 +1110,7 @@ (define_insn "@gpr_multi_push_up_to_ra_<mode>"
> (match_operand 0 "stack_push_up_to_ra_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s0_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1124,7 +1124,7 @@ (define_insn "@gpr_multi_push_up_to_s0_<mode>"
> (match_operand 0 "stack_push_up_to_s0_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s1_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1141,7 +1141,7 @@ (define_insn "@gpr_multi_push_up_to_s1_<mode>"
> (match_operand 0 "stack_push_up_to_s1_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s1}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s2_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1161,7 +1161,7 @@ (define_insn "@gpr_multi_push_up_to_s2_<mode>"
> (match_operand 0 "stack_push_up_to_s2_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s2}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s3_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1184,7 +1184,7 @@ (define_insn "@gpr_multi_push_up_to_s3_<mode>"
> (match_operand 0 "stack_push_up_to_s3_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s3}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s4_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1210,7 +1210,7 @@ (define_insn "@gpr_multi_push_up_to_s4_<mode>"
> (match_operand 0 "stack_push_up_to_s4_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s4}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s5_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1239,7 +1239,7 @@ (define_insn "@gpr_multi_push_up_to_s5_<mode>"
> (match_operand 0 "stack_push_up_to_s5_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s5}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s6_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1271,7 +1271,7 @@ (define_insn "@gpr_multi_push_up_to_s6_<mode>"
> (match_operand 0 "stack_push_up_to_s6_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s6}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s7_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1306,7 +1306,7 @@ (define_insn "@gpr_multi_push_up_to_s7_<mode>"
> (match_operand 0 "stack_push_up_to_s7_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s7}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s8_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1344,7 +1344,7 @@ (define_insn "@gpr_multi_push_up_to_s8_<mode>"
> (match_operand 0 "stack_push_up_to_s8_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s8}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s9_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1385,7 +1385,7 @@ (define_insn "@gpr_multi_push_up_to_s9_<mode>"
> (match_operand 0 "stack_push_up_to_s9_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s9}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> (define_insn "@gpr_multi_push_up_to_s11_<mode>"
> [(set (mem:X (plus:X (reg:X SP_REGNUM)
> @@ -1432,7 +1432,7 @@ (define_insn "@gpr_multi_push_up_to_s11_<mode>"
> (match_operand 0 "stack_push_up_to_s11_operand" "I")))]
> "TARGET_ZCMP"
> "cm.push {ra, s0-s11}, %0"
> -)
> +[(set_attr "type" "csr")])
>
> ;; ZCMP mv
> (define_insn "*mva01s<X:mode>"
> @@ -1443,7 +1443,8 @@ (define_insn "*mva01s<X:mode>"
> "TARGET_ZCMP
> && (REGNO (operands[2]) != REGNO (operands[0]))"
> { return (REGNO (operands[0]) ==
> A0_REGNUM)?"cm.mva01s\t%1,%3":"cm.mva01s\t%3,%1"; }
> - [(set_attr "mode" "<X:MODE>")])
> + [(set_attr "mode" "<X:MODE>")
> + (set_attr "type" "csr")])
>
> (define_insn "*mvsa01<X:mode>"
> [(set (match_operand:X 0 "zcmp_mv_sreg_operand" "=r")
> @@ -1454,4 +1455,5 @@ (define_insn "*mvsa01<X:mode>"
> && (REGNO (operands[0]) != REGNO (operands[2]))
> && (REGNO (operands[1]) != REGNO (operands[3]))"
> { return (REGNO (operands[1]) ==
> A0_REGNUM)?"cm.mvsa01\t%0,%2":"cm.mvsa01\t%2,%0"; }
> - [(set_attr "mode" "<X:MODE>")])
> + [(set_attr "mode" "<X:MODE>")
> + (set_attr "type" "csr")])
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions
2023-09-06 17:50 ` [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions Edwin Lu
2023-09-06 23:22 ` Kito Cheng
@ 2023-09-07 0:42 ` Tsukasa OI
2023-09-07 13:17 ` Jeff Law
1 sibling, 1 reply; 20+ messages in thread
From: Tsukasa OI @ 2023-09-07 0:42 UTC (permalink / raw)
To: Edwin Lu; +Cc: GCC Patches
On 2023/09/07 2:50, Edwin Lu wrote:
> This patch creates a new "zicond" type and updates all zicond instructions
> with that type.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.md: Add "zicond" type
> * config/riscv/zicond.md: Update types
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> ---
> gcc/config/riscv/riscv.md | 5 +++--
> gcc/config/riscv/zicond.md | 8 ++++----
> 2 files changed, 7 insertions(+), 6 deletions(-)
>
> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
> index 6684ad89cff..c329f55db43 100644
> --- a/gcc/config/riscv/riscv.md
> +++ b/gcc/config/riscv/riscv.md
> @@ -313,6 +313,7 @@ (define_attr "ext_enabled" "no,yes"
> ;; cbo cache block instructions
> ;; crypto cryptography instructions
> ;; csr code size reduction instructions
> +;; zicond zicond instructions
> ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler.
> ;; rdvlenb vector byte length vlenb csrr read
> ;; rdvl vector length vl csrr read
> @@ -422,8 +423,8 @@ (define_attr "type"
> mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul,
> fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,trap,ghost,bitmanip,
> rotate,clmul,min,max,minu,maxu,clz,ctz,cpop,
> - atomic,condmove,cbo,crypto,csr,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,vsetvl,
> - vlde,vste,vldm,vstm,vlds,vsts,
> + atomic,condmove,cbo,crypto,csr,zicond,rdvlenb,rdvl,wrvxrm,wrfrm,rdfrm,
> + vsetvl, vlde,vste,vldm,vstm,vlds,vsts,
> vldux,vldox,vstux,vstox,vldff,vldr,vstr,
> vlsegde,vssegte,vlsegds,vssegts,vlsegdux,vlsegdox,vssegtux,vssegtox,vlsegdff,
> vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp,viminmax,
> diff --git a/gcc/config/riscv/zicond.md b/gcc/config/riscv/zicond.md
> index 1721e1011ea..0269bd14399 100644
> --- a/gcc/config/riscv/zicond.md
> +++ b/gcc/config/riscv/zicond.md
> @@ -30,7 +30,7 @@ (define_insn "*czero.<eqz>.<GPR:mode><X:mode>"
> (const_int 0)))]
> "TARGET_ZICOND"
> "czero.<eqz>\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
> (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
> [(set (match_operand:GPR 0 "register_operand" "=r")
> @@ -40,7 +40,7 @@ (define_insn "*czero.<nez>.<GPR:mode><X:mode>"
> (match_operand:GPR 2 "register_operand" "r")))]
> "TARGET_ZICOND"
> "czero.<nez>\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
> ;; Special optimization under eq/ne in primitive semantics
> (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
> @@ -51,7 +51,7 @@ (define_insn "*czero.eqz.<GPR:mode><X:mode>.opt1"
> (match_operand:GPR 3 "register_operand" "r")))]
> "TARGET_ZICOND && rtx_equal_p (operands[1], operands[2])"
> "czero.eqz\t%0,%3,%1"
> -)
> +[(set_attr "type" "zicond")])
>
> (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
> [(set (match_operand:GPR 0 "register_operand" "=r")
> @@ -61,7 +61,7 @@ (define_insn "*czero.nez.<GPR:mode><X:mode>.opt2"
> (match_operand:GPR 3 "register_operand" "1")))]
> "TARGET_ZICOND && rtx_equal_p (operands[1], operands[3])"
> "czero.eqz\t%0,%2,%1"
> -)
> +[(set_attr "type" "zicond")])
>
> ;; Combine creates this form in some cases (particularly the coremark
> ;; CRC loop.
Looks okay to me but will need to resolve merge conflicts after commit
af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
'Zicond' support").
Thanks,
Tsukasa
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions
2023-09-07 0:42 ` Tsukasa OI
@ 2023-09-07 13:17 ` Jeff Law
2023-09-11 17:48 ` [PATCH 3/5][Committed] " Edwin Lu
0 siblings, 1 reply; 20+ messages in thread
From: Jeff Law @ 2023-09-07 13:17 UTC (permalink / raw)
To: Tsukasa OI, Edwin Lu; +Cc: GCC Patches
On 9/6/23 18:42, Tsukasa OI via Gcc-patches wrote:
>
> Looks okay to me but will need to resolve merge conflicts after commit
> af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
> 'Zicond' support").
Sure. We allow trival updates to resolve merge conflicts without
needing another round of review.
Jeff
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/5] RISC-V: Remove Assert Protecting Types
2023-09-06 17:50 ` [PATCH 5/5] RISC-V: Remove Assert Protecting Types Edwin Lu
@ 2023-09-07 13:19 ` Jeff Law
2023-09-07 17:31 ` Edwin Lu
0 siblings, 1 reply; 20+ messages in thread
From: Jeff Law @ 2023-09-07 13:19 UTC (permalink / raw)
To: Edwin Lu, gcc-patches; +Cc: gnu-toolchain
On 9/6/23 11:50, Edwin Lu wrote:
> This patch turns on the assert which ensures every instruction has type
> that is not TYPE_UNKNOWN.
>
> gcc/ChangeLog:
>
> * config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
And this is fine. But hold off committing until all the dependencies
are also committed. I think there's still one earlier patch that I
wanted to look at again.
jeff
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 1/5] RISC-V: Update Types for Vector Instructions
2023-09-06 23:23 ` Kito Cheng
@ 2023-09-07 17:26 ` Edwin Lu
0 siblings, 0 replies; 20+ messages in thread
From: Edwin Lu @ 2023-09-07 17:26 UTC (permalink / raw)
To: Kito Cheng; +Cc: GCC Patches, gnu-toolchain
On 9/6/2023 4:23 PM, Kito Cheng wrote:
> LGTM
>
> Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:51 寫道：
>
> This patch adds types to vector instructions that were added after
> or were
> missed by the original patch
> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628594.html
>
> gcc/ChangeLog:
>
> * config/riscv/autovec-opt.md: Update types
> * config/riscv/autovec.md: likewise
>
> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
> ---
> gcc/config/riscv/autovec-opt.md | 42
> ++++++++++++++++++++++-----------
> gcc/config/riscv/autovec.md | 28 +++++++++++++++-------
> 2 files changed, 47 insertions(+), 23 deletions(-)
>
There seems to be around 9 new instructions that were added since this
patch. I have tested them for the same extensions but only for linux so
far. I'll submit a new patch later today with those changes
Edwin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions
2023-09-06 23:33 ` Kito Cheng
@ 2023-09-07 17:29 ` Edwin Lu
0 siblings, 0 replies; 20+ messages in thread
From: Edwin Lu @ 2023-09-07 17:29 UTC (permalink / raw)
To: Kito Cheng; +Cc: GCC Patches, gnu-toolchain
On 9/6/2023 4:33 PM, Kito Cheng wrote:
> csr is kind of confusing, I would suggest something like `pushpop` and
> `mvpair`.
>
Sounds good! I'll make the update.
Edwin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 5/5] RISC-V: Remove Assert Protecting Types
2023-09-07 13:19 ` Jeff Law
@ 2023-09-07 17:31 ` Edwin Lu
0 siblings, 0 replies; 20+ messages in thread
From: Edwin Lu @ 2023-09-07 17:31 UTC (permalink / raw)
To: Jeff Law, gcc-patches; +Cc: gnu-toolchain
On 9/7/2023 6:19 AM, Jeff Law wrote:
>
>
> On 9/6/23 11:50, Edwin Lu wrote:
>> This patch turns on the assert which ensures every instruction has type
>> that is not TYPE_UNKNOWN.
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.cc (riscv_sched_variable_issue): Remove assert
> And this is fine. But hold off committing until all the dependencies
> are also committed. I think there's still one earlier patch that I
> wanted to look at again.
>
> jeff
Sounds good to me. The thead instructions were the ones that haven't
been checked in yet.
Edwin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/5][Committed] RISC-V: Add Types to Un-Typed Zicond Instructions
2023-09-07 13:17 ` Jeff Law
@ 2023-09-11 17:48 ` Edwin Lu
2023-09-11 17:48 ` Edwin Lu
0 siblings, 1 reply; 20+ messages in thread
From: Edwin Lu @ 2023-09-11 17:48 UTC (permalink / raw)
To: Jeff Law, Tsukasa OI; +Cc: GCC Patches
On 9/7/2023 6:17 AM, Jeff Law via Gcc-patches wrote:
>
>
> On 9/6/23 18:42, Tsukasa OI via Gcc-patches wrote:
>
>>
>> Looks okay to me but will need to resolve merge conflicts after commit
>> af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
>> 'Zicond' support").
> Sure. We allow trival updates to resolve merge conflicts without
> needing another round of review.
>
> Jeff
>
Committed!
Edwin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 3/5][Committed] RISC-V: Add Types to Un-Typed Zicond Instructions
2023-09-11 17:48 ` [PATCH 3/5][Committed] " Edwin Lu
@ 2023-09-11 17:48 ` Edwin Lu
0 siblings, 0 replies; 20+ messages in thread
From: Edwin Lu @ 2023-09-11 17:48 UTC (permalink / raw)
To: gcc-patches; +Cc: GCC Patches
On 9/7/2023 6:17 AM, Jeff Law via Gcc-patches wrote:
>
>
> On 9/6/23 18:42, Tsukasa OI via Gcc-patches wrote:
>
>>
>> Looks okay to me but will need to resolve merge conflicts after commit
>> af88776caa20 ("RISC-V: Add support for 'XVentanaCondOps' reusing
>> 'Zicond' support").
> Sure. We allow trival updates to resolve merge conflicts without
> needing another round of review.
>
> Jeff
>
Committed!
Edwin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/5][Committed] RISC-V: Update Types for RISC-V Instructions
2023-09-06 23:23 ` Kito Cheng
@ 2023-09-11 17:48 ` Edwin Lu
2023-09-11 17:48 ` Edwin Lu
0 siblings, 1 reply; 20+ messages in thread
From: Edwin Lu @ 2023-09-11 17:48 UTC (permalink / raw)
To: Kito Cheng; +Cc: GCC Patches, gnu-toolchain
On 9/6/2023 4:23 PM, Kito Cheng via Gcc-patches wrote:
> LGTM
>
> Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:52 寫道：
>
>> This patch adds types to riscv instructions that were added or were
>> missed by the original patch
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.md: Update types
>>
>> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
>> ---
>> gcc/config/riscv/riscv.md | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>> index c329f55db43..c1cecd27815 100644
>> --- a/gcc/config/riscv/riscv.md
>> +++ b/gcc/config/riscv/riscv.md
>> @@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
>> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>> "fmv.x.w\t%0,%1"
>> [(set_attr "move_type" "fmove")
>> + (set_attr "type" "fmove")
>> (set_attr "mode" "DF")])
>>
>>
>> @@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
>> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>> "fmvh.x.d\t%0,%1"
>> [(set_attr "move_type" "fmove")
>> + (set_attr "type" "fmove")
>> (set_attr "mode" "DF")])
>>
>> (define_insn "movdfsisi3_rv32"
>> @@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
>> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>> "fmvp.d.x\t%0,%2,%1"
>> [(set_attr "move_type" "fmove")
>> + (set_attr "type" "fmove")
>> (set_attr "mode" "DF")])
>>
>> (define_split
>> --
>> 2.34.1
>>
>>
>
Committed!
Edwin
^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 4/5][Committed] RISC-V: Update Types for RISC-V Instructions
2023-09-11 17:48 ` [PATCH 4/5][Committed] " Edwin Lu
@ 2023-09-11 17:48 ` Edwin Lu
0 siblings, 0 replies; 20+ messages in thread
From: Edwin Lu @ 2023-09-11 17:48 UTC (permalink / raw)
To: gcc-patches; +Cc: GCC Patches, gnu-toolchain
On 9/6/2023 4:23 PM, Kito Cheng via Gcc-patches wrote:
> LGTM
>
> Edwin Lu <ewlu@rivosinc.com> 於 2023年9月7日 週四 01:52 寫道：
>
>> This patch adds types to riscv instructions that were added or were
>> missed by the original patch
>> https://gcc.gnu.org/pipermail/gcc-patches/2023-August/628996.html
>>
>> gcc/ChangeLog:
>>
>> * config/riscv/riscv.md: Update types
>>
>> Signed-off-by: Edwin Lu <ewlu@rivosinc.com>
>> ---
>> gcc/config/riscv/riscv.md | 3 +++
>> 1 file changed, 3 insertions(+)
>>
>> diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
>> index c329f55db43..c1cecd27815 100644
>> --- a/gcc/config/riscv/riscv.md
>> +++ b/gcc/config/riscv/riscv.md
>> @@ -2223,6 +2223,7 @@ (define_insn "movsidf2_low_rv32"
>> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>> "fmv.x.w\t%0,%1"
>> [(set_attr "move_type" "fmove")
>> + (set_attr "type" "fmove")
>> (set_attr "mode" "DF")])
>>
>>
>> @@ -2235,6 +2236,7 @@ (define_insn "movsidf2_high_rv32"
>> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>> "fmvh.x.d\t%0,%1"
>> [(set_attr "move_type" "fmove")
>> + (set_attr "type" "fmove")
>> (set_attr "mode" "DF")])
>>
>> (define_insn "movdfsisi3_rv32"
>> @@ -2247,6 +2249,7 @@ (define_insn "movdfsisi3_rv32"
>> "TARGET_HARD_FLOAT && !TARGET_64BIT && TARGET_ZFA"
>> "fmvp.d.x\t%0,%2,%1"
>> [(set_attr "move_type" "fmove")
>> + (set_attr "type" "fmove")
>> (set_attr "mode" "DF")])
>>
>> (define_split
>> --
>> 2.34.1
>>
>>
>
Committed!
Edwin
^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2023-09-11 17:50 UTC | newest]
Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed)
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2023-09-06 17:50 [PATCH 0/5] RISC-V: Add Types to Untyped Instructions Edwin Lu
2023-09-06 17:50 ` [PATCH 1/5] RISC-V: Update Types for Vector Instructions Edwin Lu
2023-09-06 23:23 ` Kito Cheng
2023-09-07 17:26 ` Edwin Lu
2023-09-06 17:50 ` [PATCH 2/5] RISC-V: Add Types for Un-Typed zc Instructions Edwin Lu
2023-09-06 23:33 ` Kito Cheng
2023-09-07 17:29 ` Edwin Lu
2023-09-06 17:50 ` [PATCH 3/5] RISC-V: Add Types to Un-Typed Zicond Instructions Edwin Lu
2023-09-06 23:22 ` Kito Cheng
2023-09-07 0:42 ` Tsukasa OI
2023-09-07 13:17 ` Jeff Law
2023-09-11 17:48 ` [PATCH 3/5][Committed] " Edwin Lu
2023-09-11 17:48 ` Edwin Lu
2023-09-06 17:50 ` [PATCH 4/5] RISC-V: Update Types for RISC-V Instructions Edwin Lu
2023-09-06 23:23 ` Kito Cheng
2023-09-11 17:48 ` [PATCH 4/5][Committed] " Edwin Lu
2023-09-11 17:48 ` Edwin Lu
2023-09-06 17:50 ` [PATCH 5/5] RISC-V: Remove Assert Protecting Types Edwin Lu
2023-09-07 13:19 ` Jeff Law
2023-09-07 17:31 ` Edwin Lu
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