* [gccwwwdocs PATCH] gcc-13/14: Mention Intel new ISA and march support
@ 2023-10-23 2:18 Haochen Jiang
2023-10-27 2:53 ` Jiang, Haochen
0 siblings, 1 reply; 2+ messages in thread
From: Haochen Jiang @ 2023-10-23 2:18 UTC (permalink / raw)
To: gcc-patches; +Cc: gerald, ubizjak, hongtao.liu
Hi all,
This patch mentions recent update for x86-64 backend, including ISAs enabled
update on previous introduced CPU and newly introduced options/ISAs/CPUs.
Ok for wwwdocs?
Thx,
Haochen
---
htdocs/gcc-13/changes.html | 8 ++++----
htdocs/gcc-14/changes.html | 19 +++++++++++++++++++
2 files changed, 23 insertions(+), 4 deletions(-)
diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html
index 10c54689..8ef3d639 100644
--- a/htdocs/gcc-13/changes.html
+++ b/htdocs/gcc-13/changes.html
@@ -579,13 +579,13 @@ You may also want to check out our
</li>
<li>GCC now supports the Intel CPU named Sierra Forest through
<code>-march=sierraforest</code>.
- The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and
- CMPccXADD ISA extensions.
+ The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
+ ENQCMD and UINTR ISA extensions.
</li>
<li>GCC now supports the Intel CPU named Grand Ridge through
<code>-march=grandridge</code>.
- The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD
- and RAO-INT ISA extensions.
+ The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD,
+ ENQCMD, UINTR and RAO-INT ISA extensions.
</li>
<li>GCC now supports the Intel CPU named Emerald Rapids through
<code>-march=emeraldrapids</code>.
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index c817dde4..4f71061f 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -186,6 +186,10 @@ a work-in-progress.</p>
<h3 id="x86">IA-32/x86-64</h3>
<ul>
+ <li>New compiler option <code>-m[no-]evex512</code> was added.
+ The compiler switch enables/disables 512 bit vector and 64 bit mask
+ register. It will be default on if AVX512F is enabled.
+ </li>
<li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
AVX-VNNI-INT16 intrinsics are available via the <code>-mavxvnniint16</code>
compiler switch.
@@ -202,6 +206,16 @@ a work-in-progress.</p>
SM4 intrinsics are available via the <code>-msm4</code>
compiler switch.
</li>
+ <li>New ISA extension support for Intel USER_MSR was added.
+ USER_MSR intrinsics are available via the <code>-muser_msr</code>
+ compiler switch.
+ </li>
+ <li>GCC now supports the Intel CPU named Clearwater Forest through
+ <code>-march=clearwaterforest</code>.
+ Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
+ SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions.
+ extensions.
+ </li>
<li>GCC now supports the Intel CPU named Arrow Lake through
<code>-march=arrowlake</code>.
Based on Alder Lake, the switch further enables the AVX-IFMA,
@@ -216,6 +230,11 @@ a work-in-progress.</p>
<code>-march=lunarlake</code>.
Lunar Lake is based on Arrow Lake S.
</li>
+ <li>GCC now supports the Intel CPU named Panther Lake through
+ <code>-march=pantherlake</code>.
+ Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
+ extensions.
+ </li>
</ul>
<!-- <h3 id="mips">MIPS</h3> -->
--
2.31.1
^ permalink raw reply [flat|nested] 2+ messages in thread
* RE: [gccwwwdocs PATCH] gcc-13/14: Mention Intel new ISA and march support
2023-10-23 2:18 [gccwwwdocs PATCH] gcc-13/14: Mention Intel new ISA and march support Haochen Jiang
@ 2023-10-27 2:53 ` Jiang, Haochen
0 siblings, 0 replies; 2+ messages in thread
From: Jiang, Haochen @ 2023-10-27 2:53 UTC (permalink / raw)
To: Jiang, Haochen, gcc-patches; +Cc: gerald, ubizjak, Liu, Hongtao
> -----Original Message-----
> From: Haochen Jiang <haochen.jiang@intel.com>
> Sent: Monday, October 23, 2023 10:18 AM
> To: gcc-patches@gcc.gnu.org
> Cc: gerald@pfeifer.com; ubizjak@gmail.com; Liu, Hongtao
> <hongtao.liu@intel.com>
> Subject: [gccwwwdocs PATCH] gcc-13/14: Mention Intel new ISA and march
> support
>
> Hi all,
>
> This patch mentions recent update for x86-64 backend, including ISAs enabled
> update on previous introduced CPU and newly introduced
> options/ISAs/CPUs.
>
> Ok for wwwdocs?
I will commit the patch if there is no objection.
Thx,
Haochen
>
> Thx,
> Haochen
>
> ---
> htdocs/gcc-13/changes.html | 8 ++++---- htdocs/gcc-14/changes.html | 19
> +++++++++++++++++++
> 2 files changed, 23 insertions(+), 4 deletions(-)
>
> diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index
> 10c54689..8ef3d639 100644
> --- a/htdocs/gcc-13/changes.html
> +++ b/htdocs/gcc-13/changes.html
> @@ -579,13 +579,13 @@ You may also want to check out our
> </li>
> <li>GCC now supports the Intel CPU named Sierra Forest through
> <code>-march=sierraforest</code>.
> - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and
> - CMPccXADD ISA extensions.
> + The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT,
> CMPccXADD,
> + ENQCMD and UINTR ISA extensions.
> </li>
> <li>GCC now supports the Intel CPU named Grand Ridge through
> <code>-march=grandridge</code>.
> - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT,
> CMPccXADD
> - and RAO-INT ISA extensions.
> + The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT,
> CMPccXADD,
> + ENQCMD, UINTR and RAO-INT ISA extensions.
> </li>
> <li>GCC now supports the Intel CPU named Emerald Rapids through
> <code>-march=emeraldrapids</code>.
> diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index
> c817dde4..4f71061f 100644
> --- a/htdocs/gcc-14/changes.html
> +++ b/htdocs/gcc-14/changes.html
> @@ -186,6 +186,10 @@ a work-in-progress.</p>
>
> <h3 id="x86">IA-32/x86-64</h3>
> <ul>
> + <li>New compiler option <code>-m[no-]evex512</code> was added.
> + The compiler switch enables/disables 512 bit vector and 64 bit mask
> + register. It will be default on if AVX512F is enabled.
> + </li>
> <li>New ISA extension support for Intel AVX-VNNI-INT16 was added.
> AVX-VNNI-INT16 intrinsics are available via the <code>-
> mavxvnniint16</code>
> compiler switch.
> @@ -202,6 +206,16 @@ a work-in-progress.</p>
> SM4 intrinsics are available via the <code>-msm4</code>
> compiler switch.
> </li>
> + <li>New ISA extension support for Intel USER_MSR was added.
> + USER_MSR intrinsics are available via the <code>-muser_msr</code>
> + compiler switch.
> + </li>
> + <li>GCC now supports the Intel CPU named Clearwater Forest through
> + <code>-march=clearwaterforest</code>.
> + Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16,
> + SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions.
> + extensions.
> + </li>
> <li>GCC now supports the Intel CPU named Arrow Lake through
> <code>-march=arrowlake</code>.
> Based on Alder Lake, the switch further enables the AVX-IFMA, @@ -216,6
> +230,11 @@ a work-in-progress.</p>
> <code>-march=lunarlake</code>.
> Lunar Lake is based on Arrow Lake S.
> </li>
> + <li>GCC now supports the Intel CPU named Panther Lake through
> + <code>-march=pantherlake</code>.
> + Based on Arrow Lake S, the switch further enables the PREFETCHI ISA
> + extensions.
> + </li>
> </ul>
>
> <!-- <h3 id="mips">MIPS</h3> -->
> --
> 2.31.1
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