From: Fei Gao <gaofei@eswincomputing.com>
To: gcc-patches@gcc.gnu.org
Cc: kito.cheng@gmail.com, palmer@dabbelt.com, jeffreyalaw@gmail.com,
Fei Gao <gaofei@eswincomputing.com>
Subject: [PATCH 4/4] [ifcvt] if convert x=c ? y&z : y by RISC-V Zicond like insns
Date: Mon, 30 Oct 2023 07:25:23 +0000 [thread overview]
Message-ID: <20231030072523.26818-5-gaofei@eswincomputing.com> (raw)
In-Reply-To: <20231030072523.26818-1-gaofei@eswincomputing.com>
Conditional and, if zero
rd = (rc == 0) ? (rs1 & rs2) : rs1
-->
and rd, rs1, rs2
czero.eqz rtmp, rs1, rc
or rd, rd, rtmp
Conditional and, if non-zero
rd = (rc != 0) ? (rs1 & rs2) : rs1
-->
and rd, rs1, rs2
czero.nez rtmp, rs1, rc
or rd, rd, rtmp
Co-authored-by: Xiao Zeng<zengxiao@eswincomputing.com>
gcc/ChangeLog:
* ifcvt.cc (noce_cond_zero_binary_op_supported): add support for and
(noce_try_cond_zero_arith): adapt for and operation.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/zicond_ifcvt_opt.c: add TCs for and operation.
---
gcc/ifcvt.cc | 60 +++++---
.../gcc.target/riscv/zicond_ifcvt_opt.c | 134 ++++++++++++++++++
2 files changed, 176 insertions(+), 18 deletions(-)
diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index 6e341fc4d4b..cfa9bc4b850 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -2911,7 +2911,7 @@ noce_try_sign_mask (struct noce_if_info *if_info)
static bool
noce_cond_zero_binary_op_supported (enum rtx_code op)
{
- if (op == PLUS || op == MINUS || op == IOR || op == XOR)
+ if (op == PLUS || op == MINUS || op == IOR || op == XOR || op == AND)
return true;
return false;
@@ -2922,7 +2922,7 @@ noce_cond_zero_binary_op_supported (enum rtx_code op)
static bool
noce_try_cond_zero_arith (struct noce_if_info *if_info)
{
- rtx target;
+ rtx target, tmp;
rtx_insn *seq;
machine_mode mode = GET_MODE (if_info->x);
rtx common = NULL_RTX;
@@ -2949,8 +2949,9 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info)
opcode = GET_CODE (a);
common = b;
z = XEXP (a, 1);
- /* x = c ? y+z : y, cond = !c --> x = cond ? y : y+z */
- czero_code = GET_CODE (cond);
+ /* x = c ? y+z : y, cond = !c --> x = cond ? y : y+z, but AND differs */
+ czero_code
+ = (opcode == AND) ? noce_reversed_cond_code (if_info) : GET_CODE (cond);
}
/* check y : y+z */
else if (noce_cond_zero_binary_op_supported (GET_CODE (b))
@@ -2960,8 +2961,9 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info)
opcode = GET_CODE (b);
common = a;
z = XEXP (b, 1);
- /* x = c ? y : y+z, cond = !c --> x = !cond ? y : y+z */
- czero_code = noce_reversed_cond_code (if_info);
+ /* x = c ? y : y+z, cond = !c --> x = !cond ? y : y+z, but AND differs */
+ czero_code
+ = (opcode == AND) ? GET_CODE (cond) : noce_reversed_cond_code (if_info);
}
else
return false;
@@ -2970,22 +2972,44 @@ noce_try_cond_zero_arith (struct noce_if_info *if_info)
return false;
start_sequence ();
+ if (opcode == AND)
+ {
+ tmp
+ = expand_simple_binop (mode, AND, common, z, NULL_RTX, 0, OPTAB_DIRECT);
+ if (!tmp)
+ {
+ end_sequence ();
+ return FALSE;
+ }
- /* If we have x = c ? x + z : x, use a new reg to avoid modifying x */
- if (common && rtx_equal_p (common, if_info->x))
- target = gen_reg_rtx (mode);
- else
- target = if_info->x;
+ target = noce_emit_czero (if_info, czero_code, common, if_info->x);
+ if (!target)
+ {
+ end_sequence ();
+ return FALSE;
+ }
- target = noce_emit_czero (if_info, czero_code, z, target);
- if (!target)
- {
- end_sequence ();
- return false;
+ target = expand_simple_binop (mode, IOR, tmp, target, if_info->x, 0,
+ OPTAB_DIRECT);
}
+ else
+ {
+ /* If we have x = c ? x + z : x, use a new reg to avoid modifying x */
+ if (common && rtx_equal_p (common, if_info->x))
+ target = gen_reg_rtx (mode);
+ else
+ target = if_info->x;
+
+ target = noce_emit_czero (if_info, czero_code, z, target);
+ if (!target)
+ {
+ end_sequence ();
+ return false;
+ }
- target = expand_simple_binop (mode, opcode, common, target, if_info->x, 0,
- OPTAB_DIRECT);
+ target = expand_simple_binop (mode, opcode, common, target, if_info->x, 0,
+ OPTAB_DIRECT);
+ }
if (!target)
{
end_sequence ();
diff --git a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c
index 3ec01dcb135..bfff570edd7 100644
--- a/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c
+++ b/gcc/testsuite/gcc.target/riscv/zicond_ifcvt_opt.c
@@ -506,3 +506,137 @@ long test_XOR_eqz_x_2(long x, long z, long c)
x = x ^ z;
return x;
}
+
+/*
+**test_AND_ceqz:
+** and a2,a1,a2
+** czero\.nez a1,a1,a3
+** or a0,a1,a2
+** ret
+*/
+// x = c ? y&z : y
+long test_AND_ceqz(long x, long y, long z, long c)
+{
+ if (c)
+ x = y & z;
+ else
+ x = y;
+ return x;
+}
+
+/*
+**test_AND_ceqz_x:
+** and a1,a0,a1
+** czero\.nez a0,a0,a2
+** or a0,a0,a1
+** ret
+*/
+// x = c ? x&z : x
+long test_AND_ceqz_x(long x, long z, long c)
+{
+ if (c)
+ x = x & z;
+
+ return x;
+}
+
+/*
+**test_AND_nez:
+** and a2,a1,a2
+** czero\.eqz a1,a1,a3
+** or a0,a1,a2
+** ret
+*/
+// x = c ? y : y&z
+long test_AND_nez(long x, long y, long z, long c)
+{
+ if (c)
+ x = y;
+ else
+ x = y & z;
+ return x;
+}
+
+/*
+**test_AND_nez_x:
+** and a1,a0,a1
+** czero\.eqz a0,a0,a2
+** or a0,a0,a1
+** ret
+*/
+// x = c ? x : x&z
+long test_AND_nez_x(long x, long z, long c)
+{
+ if (c)
+ {}
+ else
+ x = x & z;
+ return x;
+}
+
+/*
+**test_AND_nez_2:
+** and a2,a1,a2
+** czero\.eqz a1,a1,a3
+** or a0,a1,a2
+** ret
+*/
+// x = !c ? y&z : y
+long test_AND_nez_2(long x, long y, long z, long c)
+{
+ if (!c)
+ x = y & z;
+ else
+ x = y;
+ return x;
+}
+
+/*
+**test_AND_nez_x_2:
+** and a1,a0,a1
+** czero\.eqz a0,a0,a2
+** or a0,a0,a1
+** ret
+*/
+// x = !c ? x&z : x
+long test_AND_nez_x_2(long x, long z, long c)
+{
+ if (!c)
+ x = x & z;
+
+ return x;
+}
+
+/*
+**test_AND_eqz_2:
+** and a2,a1,a2
+** czero\.nez a1,a1,a3
+** or a0,a1,a2
+** ret
+*/
+// x = !c ? y : y&z
+long test_AND_eqz_2(long x, long y, long z, long c)
+{
+ if (!c)
+ x = y;
+ else
+ x = y & z;
+ return x;
+}
+
+/*
+**test_AND_eqz_x_2:
+** and a1,a0,a1
+** czero\.nez a0,a0,a2
+** or a0,a0,a1
+** ret
+*/
+// x = !c ? x : x&z
+long test_AND_eqz_x_2(long x, long z, long c)
+{
+ if (!c)
+ {}
+ else
+ x = x & z;
+ return x;
+}
--
2.17.1
next prev parent reply other threads:[~2023-10-30 7:25 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-30 7:25 [PATCH 0/4] add support for conditional zero operation Fei Gao
2023-10-30 7:25 ` [PATCH 1/4] [RISC-V]add hook to control Zicond based ifcvt opt Fei Gao
2023-10-30 15:12 ` Jeff Law
2023-10-30 7:25 ` [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns Fei Gao
2023-10-30 16:36 ` Jeff Law
2023-10-31 2:53 ` Fei Gao
2023-10-30 18:41 ` Jeff Law
2023-10-30 19:16 ` Jeff Law
2023-10-31 3:35 ` Fei Gao
2023-11-20 6:46 ` Jeff Law
2023-11-28 2:46 ` Fei Gao
2023-11-28 5:05 ` Jeff Law
2023-11-20 6:59 ` Jeff Law
2023-11-28 2:57 ` Fei Gao
2023-11-29 4:46 ` Jeff Law
2023-10-30 7:25 ` [PATCH 3/4] [ifcvt] if convert x=c ? y op z " Fei Gao
2023-11-20 7:02 ` Jeff Law
2023-10-30 7:25 ` Fei Gao [this message]
2023-10-30 18:46 ` [PATCH 4/4] [ifcvt] if convert x=c ? y&z " Jeff Law
2023-11-20 7:10 ` Jeff Law
2023-11-28 3:04 ` Fei Gao
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