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From: Jeff Law <jeffreyalaw@gmail.com>
To: Fei Gao <gaofei@eswincomputing.com>,
	gcc-patches <gcc-patches@gcc.gnu.org>
Cc: Kito Cheng <kito.cheng@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>
Subject: Re: [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns
Date: Mon, 27 Nov 2023 22:05:30 -0700	[thread overview]
Message-ID: <697a3367-659b-42e9-8ed2-4947fe72ae06@gmail.com> (raw)
In-Reply-To: <20231128104654781897135@eswincomputing.com>



On 11/27/23 19:46, Fei Gao wrote:
> On 2023-11-20 14:46  Jeff Law <jeffreyalaw@gmail.com> wrote:
>>
>>
>>
>> On 10/30/23 21:35, Fei Gao wrote:
>>
>>>> So just a few notes to further illustrate why I'm currently looking to
>>>> take the VRULL+Ventana implementation.  The code above would be much
>>>> better handled by just calling noce_emit_cmove.  noce_emit_cmove will go
>>>> through the conditional move expander.  So any improvement we make in
>>>> the expander "just work" when called from the if-converter.
>>> noce_emit_czero is used here to make sure czero insns are emited.
>>> noce_emit_cmove includes SFB and Thead movcc, which will take precedence
>>> over zicond in RISCV if enabled. Unfortunately we have products with SFB and Zicond
>>> both available and saw such conflict.
>>> And that is also the reason to add hook TARGET_HAVE_COND_ZERO
>>> in [PATCH 1/4] to disallow ineffient code emited by SFB enable and Zicond disabled case.
>> I understand what you're trying to do, but I would consider the
>> TARGET_HAVE_COND_ZERO fundamentally the wrong approach.
> Hi Jeff
> 
> Thanks for your review. I just post the new series.
> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327148.html
> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327151.html
> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327149.html
> https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg327150.html
> 
> TARGET_HAVE_COND_ZERO has been deleted.
THanks for the V2.  I'll see what I can do with them this week.  The 
series was posted prior to close of stage1, so it can still be 
integrated into gcc-14 if we get it cleaned up.

Jeff

  reply	other threads:[~2023-11-28  5:05 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-30  7:25 [PATCH 0/4] add support for conditional zero operation Fei Gao
2023-10-30  7:25 ` [PATCH 1/4] [RISC-V]add hook to control Zicond based ifcvt opt Fei Gao
2023-10-30 15:12   ` Jeff Law
2023-10-30  7:25 ` [PATCH 2/4] [ifcvt] if convert x=c ? y+z : y by RISC-V Zicond like insns Fei Gao
2023-10-30 16:36   ` Jeff Law
2023-10-31  2:53     ` Fei Gao
2023-10-30 18:41   ` Jeff Law
2023-10-30 19:16   ` Jeff Law
2023-10-31  3:35     ` Fei Gao
2023-11-20  6:46       ` Jeff Law
2023-11-28  2:46         ` Fei Gao
2023-11-28  5:05           ` Jeff Law [this message]
2023-11-20  6:59   ` Jeff Law
2023-11-28  2:57     ` Fei Gao
2023-11-29  4:46       ` Jeff Law
2023-10-30  7:25 ` [PATCH 3/4] [ifcvt] if convert x=c ? y op z " Fei Gao
2023-11-20  7:02   ` Jeff Law
2023-10-30  7:25 ` [PATCH 4/4] [ifcvt] if convert x=c ? y&z " Fei Gao
2023-10-30 18:46   ` Jeff Law
2023-11-20  7:10   ` Jeff Law
2023-11-28  3:04     ` Fei Gao

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